Genus VHDL 2008 Unconstrained array - Illegal element type for composite type. [VHDLPT-567] [read_hdl]

Hello!

I have a problem using Genus 19.11.
For a hierarchical design in VHDL I would like to use cascaded custom record types utilizing unconstrained arrays. Instances of these records shall be used for generic parameters.

The following example shows several things:
a) OK: usage of unconstrained array "t_signal_list" with elements of type std_logic_vector as port (fully constrained by generic parameter)
b) OK: usage of unconstrained array "t_natural_list" with elements of type natural as toplevel generic parameter
c) NOT OK: usage of unconstrained array "t_natural_list" with elements of type natural as hierarchical generic parameter (in t_settings_top)

Is there a way to solve this problem? E.g. by addional TCL-commands or a patch?

Thanks alot!

Best regards,
Florian


1. Example source code:
    library ieee;
    use ieee.Std_logic_1164.all;

    --------------------------------------------------------------------------------
    -- Package with own types (arrays, records)
    --------------------------------------------------------------------------------
    package types is

        type t_signal_list    is array (natural range <>) of std_logic_vector;
        type t_natural_list is array (natural range <>) of natural;
        
        type t_settings_top is record

            -- simple record member
            width_i    : positive;
            count_i    : positive;

            -- record member of own type (unconstrained array)
            init_list : t_natural_list;

        end record;

    end package types;



    --------------------------------------------------------------------------------
    -- Example of usage
    --------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    use work.types.all;

    entity d_cnn_top is
        
        -- Generics (Parameter)
        generic (
            -- top level usage of own type (unconstrained array) --> b) OK!
            p_flat_ok : t_natural_list := (1, 2, 1, 0);

            p_settings : t_settings_top := (
                                                -- simple record member
                                                width_i        =>    16,
                                                count_i        =>    16,

                                                -- record member of own type (unconstrained array) --> c) NOT OK!
                                                init_list     => (1, 2, 1, 0)
                                            )
            );

        -- Ports
        port (
                   -- Input list with specified width and item count (fully defined via t_settings_top record instance "p_settings") --> a) OK!
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.width_i-1 downto 0 );
                
                clk_i        : in     
                std_logic;
                   a_reset_l_i    : in     std_logic

            );
    end d_cnn_top;






2. Necessary TCL-commands (define usage of VHDL version 2008)
    set_db / .hdl_vhdl_read_version 2008
    read_hdl -vhdl $VHDL_SRC_LIST


3. Error log
    Information: Analyzing VHDL sources ... (GENUS-ICPRO)
      Setting attribute of root '/': 'hdl_vhdl_read_version' = 2008
                  Reading VHDL predefined package '../19.11.000/tools.lnx86/lib/vhdl/v2008/std/standard.vhdl'
                Reading VHDL file 'd_test.vhdl'
                  Reading VHDL predefined package '../19.11.000/tools.lnx86/lib/vhdl/v2008/ieee/std_logic_1164.vhdl'
                  Reading VHDL predefined package '../19.11.000/tools.lnx86/lib/vhdl/cadence/attributes.vhdl'
                  Reading VHDL predefined package '../19.11.000/tools.lnx86/lib/vhdl/v2008/std/textio.vhdl'
            init_list : t_natural_list;
                                      |
    ERROR   : Illegal element type for composite type. [VHDLPT-567] [read_hdl]
            : Element of an unconstrained array subtype in file 'd_test.vhdl' on line 21, column 29.
            : Invalid or unsupported VHDL syntax is encountered.
    Info    : Design unit not stored. [VHDLPT-506]
            : Package types.
            p_settings : t_settings_top := (
                         |
    ERROR   : Undeclared identifier. [VHDLPT-766] [read_hdl]
            : Identifier 't_settings_top' in file 'd_test.vhdl' on line 36, column 16.
            : Invalid or unsupported VHDL syntax is encountered.
            p_settings : t_settings_top := (
                                           |
    ERROR   : The default expression of an interface object must be static. [VHDLPT-697] [read_hdl]
            : in file 'd_test.vhdl' on line 36, column 34.
            : Invalid or unsupported VHDL syntax is encountered.
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                              |
    ERROR   : Undeclared identifier. [VHDLPT-766] [read_hdl]
            : Identifier 't_signal_list' in file 'd_test.vhdl' on line 49, column 25.
    Info    : Too many issues in the source RTL. [VHDLPT-515]
            : .
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                                           |
    ERROR   : Missing token. [VHDLPT-672] [read_hdl]
            : array constraint requires ')', read '(' in file 'd_test.vhdl' on line 49, column 38.
            : Invalid or unsupported VHDL syntax is encountered.
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                                           |
    ERROR   : Missing token. [VHDLPT-672] [read_hdl]
            : port clause requires ')', read '(' in file 'd_test.vhdl' on line 49, column 38.
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                                           |
    ERROR   : Missing token. [VHDLPT-672] [read_hdl]
            : port clause requires ';', read '(' in file 'd_test.vhdl' on line 49, column 38.
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                                           |
    ERROR   : Statement in declarative part. [VHDLPT-752] [read_hdl]
            : in file 'd_test.vhdl' on line 49, column 38.
            : Invalid or unsupported VHDL syntax is encountered.
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                                            |
    ERROR   : Missing token. [VHDLPT-672] [read_hdl]
            : entity declaration requires END, read <identifier> p_settings in file 'd_test.vhdl' on line 49, column 39.
                   datalist_i        : in     t_signal_list(p_settings.count_i-1 downto 0 )(p_settings.len_i-1 downto 0 );
                                                                      |
    ERROR   : Missing token. [VHDLPT-672] [read_hdl]
            : entity declaration requires ';', read '.' in file 'd_test.vhdl' on line 49, column 49.
    Info    : Design unit not stored. [VHDLPT-506]
            : Entity d_cnn_top.
    Info    : Summary of VHDL issues. [VHDLPT-508]
            : 10 errors and 8 warnings reported.
    #@ End verbose source scripts/generic.tcl