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  3. CML driver phase noise

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CML driver phase noise

vinodjn
vinodjn over 1 year ago

Hi,

I have CML driver whose output feed to offchip SSA (phase noise analyzer).

I am simulating CML driver phase noise to correlate it with SSA measurement.

CML is PMOS differential amplifier with resistive load, whose output is 0-250mV single ended (+/-250mV differential).

1). sampled jitter phase noise simulation output

2) Time average phase noise simulation output

I thought sampled jitter is correct way for CML driver, however SSA  jitter correlate to time average phase noise.

 which method is correct for CML driver phase noise? 

Thanks,

Vinod

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  • ShawnLogan
    ShawnLogan over 1 year ago in reply to ShawnLogan

    Dear Vinod,

    I remained puzzled about your time-averaged pnoise result. Therefore, I took some time to study amplitude modulated periodic square waves at 25 MHz and 200 MHz  amplitude modulated by a 1/f random noise source. The study of the Fourier components of the waveforms and their respective phase noise and jitter is consistent with my understanding and not consistent with your simulation results. The note is at:

    I cannot post the item without it being classified as spam. However, you may cut and paste the following in your browser if you are interested. The summary, page 28, is attached to save you some time if you do happen to be interested.

    1drv.ms/b/

    s!AnM-GsAEZPoSr1O_-tIAqe5JG-zv?e=yKAW5I

    Shawn

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