PLL Verification RAK - Total Phase Noise

Dear Andrew,

Andrew Beckett said:

Anyway, the key here (to JJ's last questions) are that whilst the models are the same, the parameters are not. I adjusted the CDF settings so that both instances can show their parameters in the property assistant at the same time:

Thank you for both taking your valuable to review my comments and provide the verilog-A pfd/cp model parameters! I suspected the default model parameter values were replace with instance based parameters and had asked Mr. JoJak Nap to confirm that.

However, the values you provided are not consistent with the simulated PFD_CP noise contribution to the PLL shown in the figure on page 60 of the note. Something is stll amiss. I computed the noise contribution of the PFD_CP to the PLL using its transfer function (from the RAK, page 14) and its charge pump gain and divider using your parameters and updated the note to v1.2 with the result. I also determined the set of model parameters whose noise contribution does correlate well with PFD-CP noise contribution on page 60. Slide 25 of the updated note contains the result and is included below if you are interested.

Shawn

Slide 25 from v1.2 of note at

Shawn,

I'm not going to try to work out what you've done differently from the workshop - but it appears that you're not taking into account the transfer functions from the point the noise is injected into the circuit to the output (there are s-domain models of each block). Comparing your working from extracting curves from graphs in a PDF, into a spreadsheet, and to the output - there's just too much scope for a discrepancy somewhere along the way and I'm afraid I don't have the time to check your working (I started to, but decided there were better things to spend my holiday weekend on...).

Suffice to say, that the noise contributions are indeed the values specified on the instance and if I turn on noise separation, I can see the noise at source versus the output noise contributions - here I've overlaid those versus the output noise:

I would encourage the original poster that if they have any questions, please contact customer support - having access to the actual data here is key to accuracy. There may of course be errors in the workshop instructions or the models, but reverse engineering things from partial information from the PDFs is not the right way to get to the bottom of any potential issues (assuming there are any issues).

Andrew

Dear Andrew,

Andrew Beckett said:

I'm not going to try to work out what you've done differently from the workshop - but it appears that you're not taking into account the transfer functions from the point the noise is injected into the circuit to the output (there are s-domain models of each block).

I am so sorry and never intended that you work out the differences!

I am actually taking into the transfer function from the point of noise injection using the gain of the phase detector and the divider. I am also not using spreadsheets to compute the contributions from the extracted data, but tools I have for signal and PLL analysis.

I was only trying to provide my analysis for JoJakNap. I agree that JoJakNap should contact customer support to discuss the issue and, if necessary, provide feedback for any possible corrections or updates. I am certainly no longer able to do this...and never intended that you would or should!

Irrespective of this, and you are curious, if you just examine the noise component of the PFD_CP to the output noise at low frequencies (say 100 Hz), it matches the output noise and reference source noise and has a value on the order of -50 dB (V^2/Hz expressed in dB). This does not make sense for a 1 Hz 1/f noise component of 10 ^(-192.9/10) even with the divider of 124 and phase detector gain.

Nuff said, I apologize for wasting your valuable time.

Shawn

ShawnLogan said:

Irrespective of this, and you are curious, if you just examine the noise component of the PFD_CP to the output noise at low frequencies (say 100 Hz), it matches the output noise and reference source noise and has a value on the order of -50 dB (V^2/Hz expressed in dB). This does not make sense for a 1 Hz 1/f noise component of 10 ^(-192.9/10) even with the divider of 124 and phase detector gain

Whilst it's been a while since I last designed a PLL, I struggle to see why the noise contribution from the PFD_CP to the output of the PLL (the VCO output) would have a gain path through the divider and the phase detector rather than through the LP/LPF and VCO. Maybe there's something I'm missing here, but the simulation results all appear reasonable to me - that a noise source for the PFD_CP goes through the gain of the LP/LPF and VCO to reach the measured noise output at ph_out.

Anyway, need to spend time on other things now that I'm back after the holidays.

Andrew