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VerilogA blind to DC sweep analysis

NewScreenName

I am trying to use a verilogA model of a continuous time comparator, so I could see the output comparison even for DC analysis. However while it works fine for basic DC, when I enable a sweep variable, even when plotting the output of the comparator as a DC sweep VS("/outp"), in facts for each point of the sweep just the DC output (without sweeping) is shown, as if it was displaying VDC("/outp") rather than VS("/outp").

Just to double check that the issue is not in my setup I tried to replace the comparator verilogA model with a vcvs from abnalogLib, and that works properly for the DC sweep, therefore I guess there is some limitation in verilogA from supporting DC sweep, or should I just write down differently the VerilogA code (which you can find below)?

module ct_comp(inp, inm, outp, outm, vdd, vss);
input inp, inm;
output outp, outm;
inout vdd, vss;
electrical inp, inm, outp, outm, vdd, vss;

real Vop, Vom;

analog begin

@ ( initial_step ) begin

Vop = V(inp) > V(inm) ? V(vdd) : V(vss);
Vom = V(inp) > V(inm) ? V(vss) : V(vdd);

end

@ (cross( V(inp) - V(inm))) begin
if(V(inp) > V(inm)) begin
Vop = V(vdd);
Vom = V(vss);
end
else begin
Vop = V(vss);
Vom = V(vdd);
end
end

V(outp) <+ transition(Vop, 10p, 10p, 10p);
V(outm) <+ transition(Vom, 10p, 10p, 10p);
end
endmodule

  • in reply to NewScreenName
    NewScreenName said:
    Then just for my understanding, is it correct that the DC sweep points should be considered as steps as well as time points are steps in a transient simulation, such that for a verilog block to "re-trigger", it is necessary to have a sort of "clocking" signal from one sweep point to the other?

    No, not really. If the code had been at the top level of the analog block and not within an event (the body of an @() operator) then it would have been executed at every point in a DC and at every tilmestep.  It was only because you wanted the code which computed the output voltage to be triggered by a clocked event in the transient but not in the DC sweep that I created a pseudo-event (toggling at each DC sweep point) - the if (analysis("dc")) toggle=1-toggle; line is executed at every DC sweep point and every timestep but doesn't do anything in the transient because of the condition.

    NewScreenName said:
    In your example you did change the vclk voltage (which if I understood correctly is the dc voltage of the generator connected to the "update" pin).

    That was only needed in the earlier version which was being triggered by the @(above(V(update)-vth))... code - it needed the update pin to change during the DC sweep to trigger the block which computed the output. In the final version above, it isn't dependent upon any signal changing during the DC sweep, and so will respond to any of the 20 bit inputs changing during the DC sweep. During the transient, it requires the update pin to be above the threshold (on rising edge only).

    NewScreenName said:
    While I had assumed initial_step would be re-computed at the beginning of each DC sweep point (assumed it was considered a time step), which is obviously wrong.

    The initial_step is only computed at the first point of any analysis (in small-signal analyses it's at the static (DC op) that's run before the small-signal analyses), and not at any time sweep or DC sweep points, as you found.

    Hope that helps clarify things!

    Andrew 

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