According to JEDEC DDR2/DDR3 layout guidelines, the routing of signals has to follow certain topologies, but can I disregard those and just put the delay skew between datelines and differential signals into the constraint manager. Also I constraint all the DRAM signals with 50 ohm impedance as to match the impedance.
Once I put in those contrasts(impedance, delay skews, setup/hold time) and I let the auto router to take care of everything.
Would this approach work without following the JEDEC recommended topologies?
hello! where's cadence support hiding at? better come out you little rat!
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