Power Amplifier Design Problems

Recently, I design a class E power ampifier circuit by refering to Mr Nathan O. Sokal's article which is "Class E RF Power Amplfier". I follow the design equations and also the conventional class E power amplifier circuit (single stage) as stated in the articles mention before. The simulator that I used is cadence virtuoso simulator. Everythings are ok before doing the impedance matching. I oberserve the input an output impedance by applying the sp analysis and plot the impedance wabeform for intput and output port. After impedance matching is done (either input or output port). I found the real part of the impedance atanother port will become negative. I understand that the negative impedance will only occur when we deal with the oscillator circuit. What I want to ask are:

1. Is this situation caused by the gate-drain capacitance which act like a feed abck loop at the high frequency operation?

2. Can I just ignored it and what should I do in order to continue the matching process( just ignored the neagitive sign at the real part?) If this problem counld not be neglected, what should I do to solve this problem?

Informations:

loaded quality factor, QL = 5; operating frequency = 2.4 GHz; supply voltage = 1.2V;CMOS technology = 0.13 um; substrate width = 500 um. L1 = 200 nH; C1 = 290.85fF; L2 = 16.5786 nH; C2 = 352.456 fF.

Recently, I design a class E power ampifier circuit by refering to Mr Nathan O. Sokal's article which is "Class E RF Power Amplfier". I follow the design equations and also the conventional class E power amplifier circuit (single stage) as stated in the articles mention before. The simulator that I used is cadence virtuoso simulator. Everythings are ok before doing the impedance matching. I oberserve the input an output impedance by applying the sp analysis and plot the impedance wabeform for intput and output port. After impedance matching is done (either input or output port). I found the real part of the impedance atanother port will become negative. I understand that the negative impedance will only occur when we deal with the oscillator circuit. What I want to ask are:

1. Is this situation caused by the gate-drain capacitance which act like a feed abck loop at the high frequency operation?

2. Can I just ignored it and what should I do in order to continue the matching process( just ignored the neagitive sign at the real part?) If this problem counld not be neglected, what should I do to solve this problem?

Informations:

loaded quality factor, QL = 5; operating frequency = 2.4 GHz; supply voltage = 1.2V;CMOS technology = 0.13 um; substrate width = 500 um. L1 = 200 nH; C1 = 290.85fF; L2 = 16.5786 nH; C2 = 352.456 fF.