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Checking Connectivity

Art254
Art254 over 15 years ago
Hi Everyone, I have a layout that has lots of cells put together. Between the cells they are connected through metals. For example, cell 1's metal2 is connected with cell2's metal2, and cell2 is connected with cell3 through metal7; within cell2 metal2 is connected to metal7. How do I ask Cadence to show that cell1 is connected to cell3? Thanks. Art
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  • skillUser
    skillUser over 15 years ago

    Hi Art,

    You have not really supplied many details, but one way to show or follow connectivity is through the "Mark Net" utility [Connectivity -> Nets -> Mark, if using IC61x].  Then if you click on a shape on metal2 it will propagate that connection up and down through the vias (provided that the technology file is set up correctly), highlighting the shapes as it goes.  This feature is present in both IC5141 and IC61x, but there are differences.

    If you are using VLS-XL [IC61x] (or Virtuoso Layout XL a.k.a. "VXL" from IC5141) then you can also use the probe feature (Connectivity -> XL Probe if using IC61x) which will allow you to cross probe between the schematic and the layout for the design.

    Hopefully this begins to answer the beginnings of the question asked (i.e. not all information is present, so it's the best I can do).

    Regards,

    Lawrence.

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  • skillUser
    skillUser over 15 years ago

    Hi Art,

    You have not really supplied many details, but one way to show or follow connectivity is through the "Mark Net" utility [Connectivity -> Nets -> Mark, if using IC61x].  Then if you click on a shape on metal2 it will propagate that connection up and down through the vias (provided that the technology file is set up correctly), highlighting the shapes as it goes.  This feature is present in both IC5141 and IC61x, but there are differences.

    If you are using VLS-XL [IC61x] (or Virtuoso Layout XL a.k.a. "VXL" from IC5141) then you can also use the probe feature (Connectivity -> XL Probe if using IC61x) which will allow you to cross probe between the schematic and the layout for the design.

    Hopefully this begins to answer the beginnings of the question asked (i.e. not all information is present, so it's the best I can do).

    Regards,

    Lawrence.

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