As a part of understanding how to optimize matching networks in cadence I am designing a matching network to match 10 ohm load to 50 ohms source at 6Ghz. I am using simple L matching network and I know all the equations required. I come up with the required values of L and C. Simulation shows real part of input impedance to be 50 ohms when I use ideal inductor and capacitor. Now I keep ideal capacitor and use inductor provided by tsmc 0.13um process. As expected (because of component Q) real part of input impedance is dropped to 45 ohms. I want to know how I can use cadence to automatically optimize this or any other matching network. I found that ADE GXL can be used for optimization but when I read the manual I thought it can be used for only Anlog Circuits (matching devices etc). Please let me know how I can use cadence to do the optimization of matching networks.
Thanks in Advance
You can read chapter-2 of the Virtuoso Analog Design Environment GXL User Guide on circuit optimization. It has most of the information you need to run an optimization.