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Problem in LVS checkingin Layout

Analog Design

 Hi,

     In my layout DRC checking is fine. But in layout ,when I am trying LVS checking, I am getting errors like below in attached . I am using Cadence Virtuoso .

 
         


            Assura (tm) Physical Verification Version av3.1:Production:dfII5.1.41
         


 Rules File    : /home/mudassar/RuleDecks/Assura/LVS/G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC_ASSURA-LVS-2.0-P2-EXTRACT.RUL
 Options       : -exec1 -LVS -cdslib /home/mudassar/cds.lib
 Work Directory: .
 Operating Mode: Legacy Mode is Off
     Increased use of dataReduction is On
     New hierarchical select is On

Loading tech rule set file : /home/mudassar/RuleDecks/Assura/LVS/techRuleSets
*WARNING* LIB analoglib from File /home/mudassar/cds.lib Line 43 redefines
*************************************************************

 Assura LVS of UMC 0.18um 1.8V/3.3V 1P6M MM/RF Process 
 Version 2.0 P2
 Dec. 08, 2006
 

*************************************************************

warn:   Undefined layer in dfII.
    Layer name 'VSTRES' doesn't exist, treating as an empty layer.
    VSTRES = layer("VSTRES" type("drawing"))

warn:   Undefined layer in dfII.
    Layer name 'IRAM' doesn't exist, treating as an empty layer.
    IRAM = layer("IRAM" type("drawing"))

*Error* ddGetObjReadPath: argument #1 should be a ddUserType (type template = "b") - nil
<<< Stack Trace >>>
ddGetObjReadPath(ddGetObj("analogLib" nil nil "./mtlineProcs.il"))
load(ddGetObjReadPath(ddGetObj("analogLib" nil nil "./mtlineProcs.il")))
...
*Error* ddGetObjReadPath: argument #1 should be a ddUserType (type template = "b") - nil
<<< Stack Trace >>>
ddGetObjReadPath(ddGetObj("analogLib" nil nil "./ibisProcs.il"))
load(ddGetObjReadPath(ddGetObj("analogLib" nil nil "./ibisProcs.il")))
...
*Error* ddGetObjReadPath: argument #1 should be a ddUserType (type template = "b") - nil
<<< Stack Trace >>>
ddGetObjReadPath(ddGetObj("analogLib" nil nil "./nportProcs.il"))
load(ddGetObjReadPath(ddGetObj("analogLib" nil nil "./nportProcs.il")))
...
*Error* ddGetObjReadPath: argument #1 should be a ddUserType (type template = "b") - nil
<<< Stack Trace >>>
ddGetObjReadPath(ddGetObj("analogLib" nil nil "./soiPProcs.il"))
load(ddGetObjReadPath(ddGetObj("analogLib" nil nil "./soiPProcs.il")))
...
*Error* ddGetObjReadPath: argument #1 should be a ddUserType (type template = "b") - nil
<<< Stack Trace >>>
ddGetObjReadPath(ddGetObj("analogLib" nil nil "./vbicProcs.il"))
load(ddGetObjReadPath(ddGetObj("analogLib" nil nil "./vbicProcs.il")))
...
warn:   LVS Run detected.
Non-legacy mode has been disabled for this LVS run
Checking out license for Assura_DRC 3.10

Reading the design data...



















Net Listing Mode is Analog
*Error* schematic cell: UWB_Modification TFF_1.2 schematic
The schematic has been modified since it was  last extracted.
Use the `Check and Save' operation in the schematics editor to correct this.
1 error(s) encountered, vldb not generated
Error - dfIIToVldb failed to execute

*WARNING* /cad/cadence/assura/tools/assura/bin/nvn exit with bad status

Finished /cad/cadence/assura/tools/assura/bin/nvn
*WARNING* Status 256
*WARNING* Assura execution terminated

*WARNING* An error occurred during Nvn PreExtraction.
LVS preprocessing requires a successful run of Nvn.
Assura will now terminate.

*WARNING* Bad exit from child process .. 0x100


*****  aveng terminated abnormally  *****



*****  aveng fork terminated abnormally  *****


*WARNING* /cad/cadence/assura/tools/assura/bin/aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated
Parents
  • Andrew Beckett

    You'd probably be better off contacting the supplier of this design kit (UMC?). My guess is that there are two problems here:

    1. The schematic you're trying to LVS contains some non-physical devices (e.g. mtline, ibis etc) - i.e. all those from analogLib. To LVS something you'll almost certainly need to use the components from the PDK.
    2.  The cellView UWB_Modification TFF_1.2 schematic needs check-and-savin.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    You'd probably be better off contacting the supplier of this design kit (UMC?). My guess is that there are two problems here:

    1. The schematic you're trying to LVS contains some non-physical devices (e.g. mtline, ibis etc) - i.e. all those from analogLib. To LVS something you'll almost certainly need to use the components from the PDK.
    2.  The cellView UWB_Modification TFF_1.2 schematic needs check-and-savin.

    Regards,

    Andrew.

Children
No Data

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