Stats

Locked Locked
Replies 0
Subscribers 63
Views 13415
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Jitter from pnoise simulation

I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps.

In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter.

My setting of pss simulation is as follow:

Beat frequency : auto Calculate, wich is 2 MHz

Number of harmonic : 10

Accuracy : Moderate

Now, my problem is in setting the pnoise analysis

1) how we set the output frequency sweep range?

2) Maximum of side band : The jitter depends strongly on this value. So how can we set it ?

3) In the main Form, when we plot the Jee, we have to set the integration limits : How can we set this.

Thanks.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.