I have a question about the LVS. I am testing a PAD layout now (both the schematic and layout are ready from the designkits), the schematic includes a "presistor" from "analogLib". But when I run LVS, I get the error because there are not related layout for the "presistor". I think the "presistor" is only used to model the parasitics.
My question is how to avoid this "presistor" when I run LVS. I heard that in spectre, there is a setting which can skip the component in LVS. Any comments are appreciated.
Which tool are you using for LVS? There are a number of different Cadence LVS tools (Dracula, Diva, Assura, PVS - possibly some other more esoteric choices), plus several from other EDA companies (e.g. Calibre, Hercules).
Note that your second paragraph doesn't make sense - there wouldn't be a setting in "spectre" (which is a circuit simulator) which affects LVS (a separate tool).
Also, which version of the IC tools are you using? (Help->About in the CIW).
Thank you for pointing me to misunderstand spectre and calibre. I am using Calibre 2010, mmsim.11.10.214, Virtuoso 22.214.171.1240.6.151 (ic5141).
Well, Calibre is not a Cadence tool. It's possible to add a property lxRemoveDevice on a component - but I think this is only supported in IC615 for auCdl netlisting which is what will be being used to get the schematic connectivity. Even then there are some issues
In IC5141, you either would need to customize the CDF to get the presistor to netlist as a ".CONNECT" statement, or probably it's simpler to use functionality in Calibre to short out the resistor - either by asking Calibre to short specific models, or resistors with a sufficiently small value. You'd have to read the Calibre documentation to find out how to do that - as it's not a Cadence tool and I don't have access to it.
Thank you very much for your information. I will read the manual of calibre.