• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. RF Design
  3. capacitor initial voltage retaining issue in cadence

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 63
  • Views 14694
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

capacitor initial voltage retaining issue in cadence

deicadencehelp
deicadencehelp over 13 years ago

Hello

 

Can anyone please help me with a very simple circuit of three capacitors in series. Attaching its netlist below:

 

 

simulator lang=spectre

global 0

// Library name: FloatingGate // Cell name: cap // View name: schematic

C8 (net5 0) capacitor c=1p ic=1

C10 (net05 0) capacitor c=1p ic=1

C11 (net5 net05) capacitor c=1p

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \

    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \

    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \

    checklimitdest=psf

tran tran stop=1 errpreset=moderate write="spectre.ic" \

    writefinal="spectre.fc" annotate=status maxiters=5

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile

element info what=inst where=rawfile

outputParameter info what=output where=rawfile

designParamVals info what=parameters where=rawfile

primitives info what=primitives where=rawfile

subckts info what=subckts  where=rawfile

saveOptions options save=allpub

 

 

Issue is:

With my knowlegde of circuit and experience on spice simulator of Tanner, I expect net5=1v and net05=1v

However, Output in cadence the voltage at net5 and net05 start with 1v and decreased exponentialy wo zero.

The capacitor is enable to retain its charge.

This issue looks simple but it is creating issue in all my designs, which are working well in TSpice.

Please help me

Hopeful for quick reply from some expert

Thanks

Garima 

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 13 years ago

    Garima,

    This is because of the gmin conductance that is added from floating nodes to ground. Nodes in reality are never entirely floating - there's always some leakage path. The issue is for a circuit simulator, that floating nodes can cause a convergence problem, because it leads to an ill-conditioned matrix (effectively there are potentially an infinite number of solutions for a floating node). To help with floating nodes and off junctions, spectre inserts a gmin conductance to ground (for floating nodes), or across the off junction. The default value of gmin is 1e-12 Siemens (i.e. 1e12 ohms) - and is explicitly stated in your netlist. With a 1pF cap, that's a 1 second time constant - hence, the decay you're seeing over a 1 second simulation. You could set gmin=0 in this case (Simulation->Options->Analog in ADE, or the simulatorOptions line in the netlist above), and you'll then get no decay, but be warned in general gmin helps avoid convergence problems (most circuit simulators do similar things; this is not unique to spectre).

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information