Phase noise to phase jitter for square waves

Dear yizh,

I have a decent amount of experience with this subject and think I may be able to help. However, I will let you be the judge of that!!

> I have to run a "PNOISE - sources" simulation in order to recieve
> phase noise, since I have to filter the phase noise before
> integrating in to extract jitter (in order to mimic a PLL / CDR
> transfer function).

Yes - this is a common way of determining the output phase noise of a VCO based PLL.

> A few papers were written on the subject, some of them state that
> the integration upper limit is Fc/2 while others state that it is a
> few Fc. I assume that it should be a few Fc if the tested wave is a
> sine wave (i.e. no harmonics appear in the phase noise) and Fc/2 if
> it is a square wave. Please correct me if so far I'm wrong.

The random portion of the VCO output phase noise is determined by the random time variation of its zero-crossings relative to its average period. As such, it is not significantly impacted by the shape of its output waveform as long its output buffers are reasonably well designed and not significant sources of random jitter. This is confirmed in my experience measuring the random phase noise of many different types of VCO (quartz based, LC based and ring). the open loop phase noise is not a strong function of the shape of the output waveform. For example, I have measured the random phase noise of a high frequency VCO with differential CML outputs using a differential to single ended balun (Picosecond Pulse Labs 5320B) as well as their low frequency outputs after a digital CMOS divider chain with negligible difference in their phase noise after accounting for the frequency difference between the two outputs. The integration limit on the phase noise extends to fc/2 where fc is the carrier frequency of your output waveform. The zero-crossings are effectively sampling the noise every 1/fc. Hence, the spectrum is a sampled waveform and the integration limit may be set to fc/2 to capture the entire spectrum - independent of the specific output waveform shape.


However, I might suggest you consider the specific application of your PLL. Many telecommunication and data standards specify the frequency limits for the jitter of a PLL frequency synthesizer used as the basis of a transmitter. These limits may be more appropriate than limits of essentially 0 Hz to fc/2 Hz. For example, a number of standards specify the random jitter over the limited frequency range of fc/1667 to fc/2. Others specify a fixed frequency range of, for example, 10 kHz to 20 MHz. Obviously, these different frequency ranges will reduce the impact of the low frequency random phase noise contribution of your VCO relative to frequency limits of essentially 0 Hz to fc/2.

> Otherwise, here is a correction that I would like to do in my
> PNOISE simulation settings: instead of mixing the noise with many
> harmonics (i.e. Maximum sideband >> 1) and then integrating up to
> Fc/2, I might set maximum sideband to 1, thus the noise will be
> mixed only with the first harmonic, such that I will see a phase
> noise as if I had a pure sine wave at the input and not a square
> wave. Then, I would integrate up to a few Fc and see a more
> accurate jitter result.

My understanding is that the parameter maxsideband is used to set the maximum frequency for noise folding. Hence, if you set it to 1, you will not accurately capture the folded noise of your VCO into the fc/2 frequency band due to the inherent sampling process of the VCO random noise. In fact, I believe it is recommended to verify that an increase in the value you choose for parameter maxsideband does not significantly impact the simulated phase noise. I will let the experts comment on this as they have far greater knowledge than I on the specific Cadence pss and pnoise algorithms.

> In my simulations I see substantial difference between the two
> options, that's why the question is very important.

However, I think the latter explains why your simulation of the open loop phase noise will vary significantly as your vary maxsideband from a value of 1 to N. Your phase noise is, in the case of 1, only capturing a very small portion of the VCO open loop random noise.

I hope this provides some help - or at least something to consider!

Shawn

Dear yizh,

I have a decent amount of experience with this subject and think I may be able to help. However, I will let you be the judge of that!!

> I have to run a "PNOISE - sources" simulation in order to recieve
> phase noise, since I have to filter the phase noise before
> integrating in to extract jitter (in order to mimic a PLL / CDR
> transfer function).

Yes - this is a common way of determining the output phase noise of a VCO based PLL.

> A few papers were written on the subject, some of them state that
> the integration upper limit is Fc/2 while others state that it is a
> few Fc. I assume that it should be a few Fc if the tested wave is a
> sine wave (i.e. no harmonics appear in the phase noise) and Fc/2 if
> it is a square wave. Please correct me if so far I'm wrong.

The random portion of the VCO output phase noise is determined by the random time variation of its zero-crossings relative to its average period. As such, it is not significantly impacted by the shape of its output waveform as long its output buffers are reasonably well designed and not significant sources of random jitter. This is confirmed in my experience measuring the random phase noise of many different types of VCO (quartz based, LC based and ring). the open loop phase noise is not a strong function of the shape of the output waveform. For example, I have measured the random phase noise of a high frequency VCO with differential CML outputs using a differential to single ended balun (Picosecond Pulse Labs 5320B) as well as their low frequency outputs after a digital CMOS divider chain with negligible difference in their phase noise after accounting for the frequency difference between the two outputs. The integration limit on the phase noise extends to fc/2 where fc is the carrier frequency of your output waveform. The zero-crossings are effectively sampling the noise every 1/fc. Hence, the spectrum is a sampled waveform and the integration limit may be set to fc/2 to capture the entire spectrum - independent of the specific output waveform shape.


However, I might suggest you consider the specific application of your PLL. Many telecommunication and data standards specify the frequency limits for the jitter of a PLL frequency synthesizer used as the basis of a transmitter. These limits may be more appropriate than limits of essentially 0 Hz to fc/2 Hz. For example, a number of standards specify the random jitter over the limited frequency range of fc/1667 to fc/2. Others specify a fixed frequency range of, for example, 10 kHz to 20 MHz. Obviously, these different frequency ranges will reduce the impact of the low frequency random phase noise contribution of your VCO relative to frequency limits of essentially 0 Hz to fc/2.

> Otherwise, here is a correction that I would like to do in my
> PNOISE simulation settings: instead of mixing the noise with many
> harmonics (i.e. Maximum sideband >> 1) and then integrating up to
> Fc/2, I might set maximum sideband to 1, thus the noise will be
> mixed only with the first harmonic, such that I will see a phase
> noise as if I had a pure sine wave at the input and not a square
> wave. Then, I would integrate up to a few Fc and see a more
> accurate jitter result.

My understanding is that the parameter maxsideband is used to set the maximum frequency for noise folding. Hence, if you set it to 1, you will not accurately capture the folded noise of your VCO into the fc/2 frequency band due to the inherent sampling process of the VCO random noise. In fact, I believe it is recommended to verify that an increase in the value you choose for parameter maxsideband does not significantly impact the simulated phase noise. I will let the experts comment on this as they have far greater knowledge than I on the specific Cadence pss and pnoise algorithms.

> In my simulations I see substantial difference between the two
> options, that's why the question is very important.

However, I think the latter explains why your simulation of the open loop phase noise will vary significantly as your vary maxsideband from a value of 1 to N. Your phase noise is, in the case of 1, only capturing a very small portion of the VCO open loop random noise.

I hope this provides some help - or at least something to consider!

Shawn