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Modelling White noise using VerilogA

RFStuff

 Dear All,

I want to add a cyclostaionary noise current  ( 4*k*T*Gm(t) ) to a non-linear ( hard-limiter ) Gm block

 Gm(t) = derivative( I(out)/V(in)).

But the moment I am doing  Gm_t = ddx(I(out),V(in)); It is giving error.

Actullay, I ideally want to add white_noise(4*k*T*Gm_t) to I(out) finally.

It looks recursive. But could anybody please tell how this can be done.

The code is as given below.

 

Kind Regards,

 

 

 

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"
`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);
  inout in,out;
  parameter real vtrans = 0;
  parameter real tdelay = 0 from [0:inf);
  parameter real trise = 1p from (0:inf);
  parameter real tfall = 1p from (0:inf);
  parameter real Gm=-5m;

  real Gm_t;


  electrical in,out;
  real vout_val;


  analog begin 
      @ (cross(V(in) - vtrans)) ;
     vout_val = V(in)>vtrans; 
     I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); 

     Gm_t = ddx(I(out),V(in)); // HERE IT IS SHOWING ERROR

      // Actullay, here, I ideally want to add white_noise(4*k*T*Gm_t) to I(out) .

  end   
endmodule

  • I  thought to create another block which senses the current "I1" input and voltage 'Vin" input and find the derivaive (dI1/dVin).

    To test the individual block I gave a  sine current source of 1.02GHz, amp=10mA to input I1 and a sine volatge source of  to input 'Vin" of 1GHz and amp=1V.

    But in the code it always evaluates  (dI1/dVin) ( Gm_t in the code ) to ZERO.

    Can anybody tell what is the issue ?

     

    My code is as below:-

     / VerilogA for VERILOG_A_MODEL, GM_T_NOISE, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module GM_T_NOISE(in_v,in_i,out,vx);
           inout in_v,in_i,out,vx;


           real Gm_t;


           electrical in_v,in_i,out,vx;


             analog begin
                  Gm_t=ddx(I(in_i),V(in_v));


                 I(out) <+ Gm_t;


              $strobe("GM = %rs \n", Gm_t);


              V(in_i,vx) <+ 0;  // To make short between in_i & vx

                                      // During simulation node ' vx ' is connected to ground


             end
              
        

    endmodule

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