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  3. pnoise spurs at multiples of clock frequency.

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pnoise spurs at multiples of clock frequency.

vamshiky
vamshiky over 11 years ago

Hi,

 I have a simple inverter driven by a square wave, and ran pnoise on the circuit.

There is flicker and thermal noise and after that  has huge spurs ( about +20dBc ) at 2*Ffref , 5*Fref.

And this goes away if I carefully choose the sweep type and step size (delberately avoiding those freq points during sim). 

 

Also I have noticed from earlier posts that while running pnoise sim, simulator automatically skips the freq point which is exact multiple of beat frequency and gives a message "Infinite flicker noise is ignored"

however I dont see this happening in my sims.

Are there any additonal settings/options which I missed out.

 

Thanks,

Vamshi 

 

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  • ManuelSuarez
    ManuelSuarez over 9 years ago
    hi Smlogan,

    Thanks by your answer. My case is a clock of 100MHz for an ADC and the specification was: Jitter < X fsRMS. I am interested in all contribution to the jitter so I took a large bandwidth in spite of the low frequencies has no impact.

    As you mentioned, several other answers in the forum recommend do the integration to fs/2. In the cadence documentation "FM jitter measurement ussing PSS shooting and pnoise jitter" (i use the jitter PM option) uses fs=1.9GHz and integration to 1GHz. Nevertheless, the white noise in my simulations is limited to the 1GHz where it decreases. Since we are analyzing periodic noise, i guess it has sense consider the freq=+-fs/2 only.

    I am new in the phase noise analysis and my knowledge is reduce to i read recently. In many "phase noise to jitter" tutorial, they integrate the noise in ranges from kHz to 2fs. At this point i am a little confused. The JcRMS(2fs) is close to 2JcRMS(fs/2) in the simulations, and more when I increase the bandwidth. The Jc calculated in cadence takes in to account the factor 2 of both sides of the noise around fs?

    The effects of the power supply i have to simulate them with the PXF right?

    Thanks
    M
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  • ManuelSuarez
    ManuelSuarez over 9 years ago
    hi Smlogan,

    Thanks by your answer. My case is a clock of 100MHz for an ADC and the specification was: Jitter < X fsRMS. I am interested in all contribution to the jitter so I took a large bandwidth in spite of the low frequencies has no impact.

    As you mentioned, several other answers in the forum recommend do the integration to fs/2. In the cadence documentation "FM jitter measurement ussing PSS shooting and pnoise jitter" (i use the jitter PM option) uses fs=1.9GHz and integration to 1GHz. Nevertheless, the white noise in my simulations is limited to the 1GHz where it decreases. Since we are analyzing periodic noise, i guess it has sense consider the freq=+-fs/2 only.

    I am new in the phase noise analysis and my knowledge is reduce to i read recently. In many "phase noise to jitter" tutorial, they integrate the noise in ranges from kHz to 2fs. At this point i am a little confused. The JcRMS(2fs) is close to 2JcRMS(fs/2) in the simulations, and more when I increase the bandwidth. The Jc calculated in cadence takes in to account the factor 2 of both sides of the noise around fs?

    The effects of the power supply i have to simulate them with the PXF right?

    Thanks
    M
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    • Vote Up 0 Vote Down
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