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pnoise spurs at multiples of clock frequency.

vamshiky

Hi,

 I have a simple inverter driven by a square wave, and ran pnoise on the circuit.

There is flicker and thermal noise and after that  has huge spurs ( about +20dBc ) at 2*Ffref , 5*Fref.

And this goes away if I carefully choose the sweep type and step size (delberately avoiding those freq points during sim). 

 

Also I have noticed from earlier posts that while running pnoise sim, simulator automatically skips the freq point which is exact multiple of beat frequency and gives a message "Infinite flicker noise is ignored"

however I dont see this happening in my sims.

Are there any additonal settings/options which I missed out.

 

Thanks,

Vamshi 

 

Parents

  • Dear Manuel,

    Thank you for your added application information. It is helpful!

    > My case is a clock of 100MHz for an ADC and the specification was: Jitter < X fsRMS.

    > I am interested in all contribution to the jitter so I took a large bandwidth in spite of the low frequencies has no impact..

    If you are using a 100 MHz A/D, the signal frequencies of interest must be well under 50 MHz. However, it is possible that the bandwidth of the ADC clock input may exceed the bandwidth of the input signal. If you happen to know the bandwidth of the ADC clock input, I might propose using that bandwidth as the maximum frequency to use in your clock jitter computation.

    If you have simulated the random phase noise component of a your clock signal, you can estimate its random jitter component by integrating the phase noise between the minimum and maximum frequencies of interest to compare to your requirement.

    > The effects of the power supply i have to simulate them with the PXF right?

    As far as deterministic jitter components are concerned, for the clock path you are simulating, you might impose the amount of supply noise you expect on the buffer supplies and examine the resulting peak-to-peak time interval error (TIE) at the ADC input port. This will provide an estimate of the deterministic jitter. There is some frequency dependence to the peak-to-peak output TIE - so the frequency content of your supply noise is important to include in the simulation. This simulation can be a simple transient simulation. 

    I hope this provides some help...

    Shawn

Reply

  • Dear Manuel,

    Thank you for your added application information. It is helpful!

    > My case is a clock of 100MHz for an ADC and the specification was: Jitter < X fsRMS.

    > I am interested in all contribution to the jitter so I took a large bandwidth in spite of the low frequencies has no impact..

    If you are using a 100 MHz A/D, the signal frequencies of interest must be well under 50 MHz. However, it is possible that the bandwidth of the ADC clock input may exceed the bandwidth of the input signal. If you happen to know the bandwidth of the ADC clock input, I might propose using that bandwidth as the maximum frequency to use in your clock jitter computation.

    If you have simulated the random phase noise component of a your clock signal, you can estimate its random jitter component by integrating the phase noise between the minimum and maximum frequencies of interest to compare to your requirement.

    > The effects of the power supply i have to simulate them with the PXF right?

    As far as deterministic jitter components are concerned, for the clock path you are simulating, you might impose the amount of supply noise you expect on the buffer supplies and examine the resulting peak-to-peak time interval error (TIE) at the ADC input port. This will provide an estimate of the deterministic jitter. There is some frequency dependence to the peak-to-peak output TIE - so the frequency content of your supply noise is important to include in the simulation. This simulation can be a simple transient simulation. 

    I hope this provides some help...

    Shawn

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