HBAC analysis issue, while simulating a mixer from Cadence examples

Can you post the bottom part of the input.scs file - all the lines from below the circuit to the end (i.e. the options statement, and all the analysis statements)? Also can you say which subversion of the IC tools (Help->About in the CIW) you're using, and also the precise spectre version (this will appear at the top of the spectre.out file you are seeing with the error messages above)?

Thanks,

Andrew.

Hello.

Here is the content of the input.scs:

 simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
sweephb  sweep  param=plo  start=-10  stop=20  step=3  {
  hb  hb  oversample=[1]  funds=["FLO"]  maxharms=[8]
+   errpreset=moderate  tstab=1n  annotate=status

  hbac  hbac  start=5001  M  maxsideband=8  annotate=status
}

modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub
ahdl_include "/cadence/2012_2013/ic5/tools/dfII/samples/artist/rfLib/balun/veriloga/veriloga.va"

Subversion of the IC tools is as follows:

 Virtuoso (R) Front to Back Design Environmnet 5.10.41.500.6.151

Spectre.out claims the following:

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 11.1.0.509.isr14 32bit -- 14 Aug 2012

Thank you for your time and effort.

 Hm...

I guess I found the problem... There was a space between 5001 and M... which, it seems,  made the software think something else, instead of 5001 MHz, i.e. 5.001 GHz.

So I put the following 5.001G and now I have it running... Sorry for bothering about a stupid typo - I apologize for wasting time.

Nevertheless, I have another question. What is a master.tag file?

Namely, when I was putting together the test bench from the Mixer example, I was asked to put a component called balun_ideal. When I put - I could not run the damn thing. A colleage of mine told me that I need to create a new view (config) and the I will be able to run simulations of a schematic containing components from rfLib. But, when I try to do so, I get the following message:

Warning: The cellview (rfLib balun_ideal veriloga) may exist, but the master.tag is bad, or the view's master was not found.

Why config view must be created, in the first place (the colleague just saw it done - he didn't know why)? And what does master.tag do and what does it mean "it's bad"?

When I use component "balun" instead of "balun_ideal", I can successfully create the config view, and then the simulation runs - that's how I kno that the config-trick works.

Thank you for you time and effort.

The "master.tag" file is a file that lives within the cellView directory which tells Virtuoso which file is the "master" file for the cellView, and hence what type of view it is. So here's an example (from ahdlLib):

UNIX> pwd
/export/home/apps/IC616_isr/tools/dfII/samples/artist/ahdlLib/decimator/veriloga
UNIX> ls -lL
total 24
-rw-r--r-- 1 workmgr users    40 Nov  8  1996 master.tag
-rw-r--r-- 1 workmgr users 13128 Apr  9  2007 netlist.oa
-rw-r--r-- 1 workmgr users     0 Sep  8  1997 pc.db
-rwxr-xr-x 1 workmgr users  1453 Jul 31  2004 veriloga.va*
UNIX> cat master.tag
-- Master.tag File, Rev:1.0
veriloga.va

As  you can see in this cellView, there is a "netlist.oa" file - this contains some information about the veriloga view, such as the terminals and hierarchy (none in this case) of the design - which is used to help with hierarchy traversal.

Just realised that would have made more sense to show the balun_ideal cellView as an example, but the master.tag is identical (in my installation).

Adding a config view won't help if the master.tag is messed up. It shouldn't be required for spectre simulation anyway - all that allows you to do is have more fine-grained control over view-switching during netlisting. WIthout a config view, you can simply control the switch (or view) list and stop list. The view list gives  you the order of preference for picking a view when descending the hierarchy, and the stop list says that if the view you switched into was in the stop list, don't expand the hierarchy any further. With a config, you can tell it that specific cells or instances (or occurrences) can use a different view than the global search order, or you can have an inherited view order for that part of the hierarchy downwards and so on.

So the "config trick" is not a trick - and it's not really relevant here (I don't think). You need to look in the balun_ideal/veriloga directory and see if the master.tag is missing or messed up - if so, it may be something has got corrupted in your installation:

UNIX> pwd
/export/home/apps/IC616_isr/tools/dfII/samples/artist/rfLib/balun_ideal/veriloga
UNIX> ls -lL
total 32
-rw-r--r-- 1 workmgr users  2720 Apr 20  2009 data.dm
-rw-r--r-- 1 workmgr users    40 Apr 20  2009 master.tag
-rw-r--r-- 1 workmgr users 13080 Apr 20  2009 netlist.oa
-rwxr-xr-x 1 workmgr users   479 Apr 20  2009 verilog.vams*
-rwxr-xr-x 1 workmgr users   479 Apr 20  2009 veriloga.va*

Note that if you are using IC5141, the files may be slightly different (prop.xx and veriloga.cdb). Ah, I just took a look in my IC5141 installation and it seems that the balun_ideal veriloga view directory is empty.

So maybe that is your problem? I'm really not sure why it was missing - strangely I can't find any reports of it being missing (despite the fact that it was for some time).

Which version are you using?

Regards,

Andrew.

 Hello.

Thank you for a through explanation and sorry for a late answer - some paperwork needed to be taken care of.

I ventured into the rfLib folder and there I found both balun and balun_ideal. Each of these has two folders (symbol and veriloga) and prop.xx. The symbol folders for each look the same: they both contain a master.tag file which are identical. Nevertheless, the difference appears in balun_ideal/veriloga folder - it's empty! On the other hand balun/verliga contains master.tag, pc.db, veriloga.cd%, veriloga.cdb and veriloga.va. So - this is where the error was coming from.

Is there a way for me to obtain the missing files? 

Or, can I just keep using balun instead of balun_ideal? As far as I can see, the only difference is that balun_ideal has an offset input port - so if I give a DC voltage offset to the input signal of balun - should it make at least they look the same?

As far as the sofware version is considered, here it is:

icfb -W
sub-version 5.10.41.500.6.151

Regards.

I don't want to post it here because it is copyrighted material (although it's not that complex), but what you could do is look in an IC615 or IC616 installation at the same path - and see the veriloga.va file in the balun_ideal view there.

Then copy the balun_ideal you have in IC5141 into your own library, and do File->New->CellView and create a new veriloga view for your copied balun_ideal cell, and paste in the code you found in the IC616 installation into the editor. Save and quit the editor.

That should then give you the balun_ideal but working in IC5141.

Regards,

Andrew.

Thank you for your time.

I don't have a IC6 installation, but I will check with a colleague.

Thank you for your effort.

Regards.

You could also try the ideal_balun from analogLib. See http://www.designers-guide.org/analysis/diff.pdf for an explanation how it works and how you can build it yourself if necessary.