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Strange simulation results about transient jitters of inverter's input and output

bjbit

Hi all,

I designed a cross-coupled LC oscillator with a few stages of inverters following its output. From PSS+Pnoise simulations I notice that the plotted jitter at the inverter output is smaller than the oscillator output (inverter input). In general thinking, the signal jitter should increase by the noise from additional circuits, right?

To double check it, I build another simple circuit. A noisy sinusoid voltage source connects to a inverter chain. The simulation shows the same result that inverter output jitter < input jitter. The technology is IBM_CMOS_7RF(180nm). Simulator environment is IC615+MMSIM13. I attach a screenshot of the simulation settings. Does anybody have the similar issue before? Please advise if any ideas. Thanks a lot.

Best regards,

bjbit 

Parents

  • Use Sweeptype absolute and a Stop Frequency of 400M (half the PSS Beat Frequency). Take a look at the noise as a function of frequency and make sure that you are using enough sweep points so that the curve is smooth.

    I would also recommend selecting fullspectrum (if you are using APS). This should allow you to set Maximum sideband to 1 and speed up your simulation.

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  • Use Sweeptype absolute and a Stop Frequency of 400M (half the PSS Beat Frequency). Take a look at the noise as a function of frequency and make sure that you are using enough sweep points so that the curve is smooth.

    I would also recommend selecting fullspectrum (if you are using APS). This should allow you to set Maximum sideband to 1 and speed up your simulation.

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