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Strange simulation results about transient jitters of inverter's input and output

bjbit

Hi all,

I designed a cross-coupled LC oscillator with a few stages of inverters following its output. From PSS+Pnoise simulations I notice that the plotted jitter at the inverter output is smaller than the oscillator output (inverter input). In general thinking, the signal jitter should increase by the noise from additional circuits, right?

To double check it, I build another simple circuit. A noisy sinusoid voltage source connects to a inverter chain. The simulation shows the same result that inverter output jitter < input jitter. The technology is IBM_CMOS_7RF(180nm). Simulator environment is IC615+MMSIM13. I attach a screenshot of the simulation settings. Does anybody have the similar issue before? Please advise if any ideas. Thanks a lot.

Best regards,

bjbit 

Parents

  • Hi Frank,

    Thanks a lot for the resources. I had wrong understandings of the parameters "relative harmonic" and "max sideband". The document you posted is very helpful on correcting my comprehension. My question is resolved.

    Best regards,

    bjbit 

Reply

  • Hi Frank,

    Thanks a lot for the resources. I had wrong understandings of the parameters "relative harmonic" and "max sideband". The document you posted is very helpful on correcting my comprehension. My question is resolved.

    Best regards,

    bjbit 

Children
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