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  3. [help] pll simulation in spectre

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[help] pll simulation in spectre

reddevil011
reddevil011 over 11 years ago

I am trying to run a PSS analysis of a closed-loop PLL in spectre, but encounter   converge problems.

Is it possible to run a PSS analysis of a closed-loop PLL?

thanks! 

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  • ShawnLogan
    ShawnLogan over 11 years ago

     Dear reddevil011

     

    > The ripple voltage is 400uVpp.  Is it the reason why PSS analysis has converge problems?

    I do not believe this has any bearing on your convergence issue. The ripple on the control voltage is expected and totally normal. Perhaps you might try running a PSS analysis of the VCO at the control voltage at which it locks, separately determining the loop bandwidth (since you can determine the Kvco and you note you have done S domain analyses), and using the phase noise of the VCO, determining its resulting contribution to the output phase noise of the PLL as a function of frequency. Since you mention that the non-VCO components are all ideal, the only other output contribution to the PLL phase noise will be the deterministic jitter associated with the magnitude and frequency of the control voltage "ripple".

     

    This might help you get an answer with less trouble....but is only a thought after reading your post.

    Shawn

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  • ShawnLogan
    ShawnLogan over 11 years ago

     Dear reddevil011

     

    > The ripple voltage is 400uVpp.  Is it the reason why PSS analysis has converge problems?

    I do not believe this has any bearing on your convergence issue. The ripple on the control voltage is expected and totally normal. Perhaps you might try running a PSS analysis of the VCO at the control voltage at which it locks, separately determining the loop bandwidth (since you can determine the Kvco and you note you have done S domain analyses), and using the phase noise of the VCO, determining its resulting contribution to the output phase noise of the PLL as a function of frequency. Since you mention that the non-VCO components are all ideal, the only other output contribution to the PLL phase noise will be the deterministic jitter associated with the magnitude and frequency of the control voltage "ripple".

     

    This might help you get an answer with less trouble....but is only a thought after reading your post.

    Shawn

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