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  3. Rigid branches error in post-layout with RCLK

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Rigid branches error in post-layout with RCLK

RAO VINAY
RAO VINAY over 11 years ago

I have attached layout of the cascode LNA. Left most is LG, top one is LD and bottom one is LS. Whenever I try to move LS and LD away from their place and away from each other, the following error appears for post-layout s-parameter simulation after RLCK extraction. This error also appears whenever I try to change the capacitor associated with those nodes net 34:38.

"Notice from spectre during topology check.Only one connection to the following 4 nodes:

I0.net34 I0.net35 I0.net38 I0.4\:GND

No DC path from node `I0.net34' to ground, Gmin installed to provide path.

No DC path from node `I0.net35' to ground, Gmin installed to provide path.

No DC path from node `I0.net38' to ground, Gmin installed to provide path.

Fatal error found by spectre during topology check.

FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:

I0.VR2_15:p (from I0.IN#23RLJUNC15TR0 to I0.IN#23RLJUNC15TR98)"


What is the reason for this and how it can be resolved?

 

Regards,

Vinay

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Vinay,

    The error means that the simulator has found either voltage sources or inductors in parallel. It might be an issue with the extraction tool, or it might be that in conjunction with your testbench. Seeing a picture of the layout is not enough to determine what the problem is - we'd need to see the whole story.

    So please contact customer support - it may be an issue that's been fixed (you didn't mention the tool versions you're using - particularly the extraction tool) - but either way, this needs investigation in more detail than makes sense on the forums.

    Regards,

    Andrew.

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  • RAO VINAY
    RAO VINAY over 11 years ago

     Hello Andrew,

              Thanks for the reply. I am using following versions.

    IC-614 06.14.512 RHEL4 (lnx86)

    Assura-614 04.12.003 RHEL4 (lnx86)

    EXT 10.1.1

    I am not changing any of the circuit elements. I am just trying to move away Ld and Ls to avoid coupling. If I am not moving those away then post-layout simulation (in ADEL) after Assura QRC's RLCK extraction works fine. It gives error only when I am moving those away or sometimes if I am changin any components values.

     

    Regards,

    Vinay.

     

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    That's a pretty old QRC (EXT) version. I'd start with something newer such as EXT132)  to see if the issue has already been fixed. Then contact customer support if not.

    Andrew.

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