avoiding "hidden model in spectra rf" for verilog A integrator code

hi all ,

i am new in verilog a , and i had a problem while i was trying  to simulate an ADPLL simulation with the pss analysis .

as you may know the "loop filer"  in adpll i implement with an integrator  on the phase, and since that i got an "hidden model" error .

i wonder if some of you can help me to fix my code, such that it will avoid form hidden model error ,or show me a better way to do it.

the error is on " accump1" which is important to me 

thanks everybody. 

my code:

 `include "constants.vams"

`include "disciplines.vams"

 module dig_loop(ick_refclk, i_pe_tdc, o_fine,);

  input                   ick_refclk;

  electrical              ick_refclk;

  input                   i_pe_tdc;                   // quantized Phase Error

  electrical              i_pe_tdc;                   // quantized Phase Error

  parameter real          pe_offset    = 0;         

  parameter real                  i_prop_coeff = 1;

  parameter real          i_int_coeff  = 1/16;

  parameter real          i_kpscale    = 1;

  parameter real          i_kiscale    = 1/16;

  parameter real          vccd         = 1.00;

 real              pe, pe_ki, pe_kp, p1, accum_p1, big_reg, fract_int;

  integer       i, fine_int_lim, fine_int, frac;

  real          kp_scale_int, ki_scale_int, clk_cnt;

analog begin

                @(initial_step)

                begin

                                accum_p1 = 64;

                                clk_cnt = 0;

                end

                pe = V(i_pe_tdc);

                ki_scale_int = (clk_cnt > 32) ? i_int_coeff : i_int_coeff + i_kiscale;

                kp_scale_int = (clk_cnt > 32) ? i_prop_coeff : i_prop_coeff + i_kpscale;

                pe_ki      = pe * ki_scale_int;

                p1         = pe_ki + accum_p1;

                pe_kp      = pe * kp_scale_int;

                big_reg    = ((pe_kp + p1)<0) ? 0 : (((pe_kp + p1)>(127.984375) ? 127.984375 :(pe_kp + p1)));

                fract_int  = $floor((big_reg-($floor(big_reg)))*64);

                fine_int   = $floor(big_reg);

                frac       = fract_int;

                @(cross(V(ick_refclk)-vccd/2,+1))

                begin

                                accum_p1 =  (p1 < 0) ? accum_p1 : ((p1 >= 128) ? accum_p1 : p1);

                                clk_cnt = clk_cnt + 1;

                $debug("At time %fpS:pe=%f, big_reg=%f, fine_int=%d,fract_int=%f p1=%f, pe_kp=%f, pe_ki=%f,kp_scale_int=%f " ,$abstime*1e12, pe, big_reg, fine_int,fract_int, p1, pe_kp, pe_ki,kp_scale_int);

                end

//***************************************************************************

//************************ OUTPUT ASSIGNMENT ********************************

//***************************************************************************

                V(o_fine) <+ transition(fine_int, 0, 20p, 20p, 20p);

end

endmodule