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  3. Verilog A module PSS analysis taking too much time

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Verilog A module PSS analysis taking too much time

duoertai
duoertai over 10 years ago

Hi

I have a verilogA module of an ideal VCO, and I want to run a PSS and PNOISE analysis to see its phase noise, but the simulation time goes to several MEGA seconds. Does anyone know why and how to deal with this?

Thanks in advance

Attached is the VCO code:


`include "discipline.h"
`include "constants.h"

module VCO_ideal( in, out );
input in;
output out;
electrical in, out;
parameter real amp = 1;
parameter real center_freq = 14G;
parameter real vco_gain = 1K;
parameter integer steps_per_period = 32;

   real phase;
   real inst_freq;
   integer resetph;

   analog begin

    inst_freq = center_freq + vco_gain * V(in);
    $bound_step (1.0 / (steps_per_period*inst_freq));

    phase=idt(inst_freq,0);
    //phase = idtmod(inst_freq,0,1);
    V(out) <+ amp * sin (2 * `M_PI * phase) + amp;
   end
endmodule

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    Not sure without seeing your testbench - you may have something there which causes a problem. However, one thing that immediately jumps out is that you are using idt() rather than idtmod(). The idt means that your phase is not periodic - it is a ramp - and so that will prevent convergence. I'm not sure why you've changed this from idtmod, which is the right way to implement an oscillator model that will work well in SpectreRF (the phase is then represented as a number between 0 and 1 where 1 corresponds to 2*pi radians). idtmod means that the phase will reset to 0 as soon as it hits 1, so it will be a periodic sawtooth.

    Regards,

    Andrew.

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