• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. RF Design
  3. ENVELOPE: Fast mode Level1 engine not recognizing bus n...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 63
  • Views 13585
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ENVELOPE: Fast mode Level1 engine not recognizing bus notation

Michele Ancis
Michele Ancis over 9 years ago

Hi,

I am using Virtuoso 6.1.6-64b.500.10 and MMSIM131_ISR10

I select the Classic (not Wireless) ENV simulation, Harmonic Balance Engine - fast Level 1, baseband method.

I have had some experience with this approach, there is generally no issue in having this to work.

However, given the nature of my schematics, it turns out very handy to have a series of units in parallel, connected through busses.

I.e., I could have Circuit_1<2:0> and Circuit_2<2:0> connected by my_net<2:0>

I am encountering two orders of problems, the latter being more annoying than the former.

For this type of simulation, one has to define a pwl source giving the baseband signal. Actually, two sources, one for the I and the other for Q part of modulation.

First Issue: if the BB source is inside Circuit_1<0>, the engine can't find it and gives this error message:

Error found by spectre during envelope following analysis `envlp'.
ERROR: Can not find one or all of instances in 'srci' or it is not pwl type source

Indeed, if one just changes the nomenclature of the source into Circuit_1_0 - for instance - therefore dropping the angular bracket notation, then the source is correctly found, no problem.

Second Issue: this is more annoying. For this type of simulation and subsequent spectral power estimations, one has to define which node voltages to save. Very similarly to the first case, the tool seems to have problems in translating signals in bus notation. If I try to save node my_net<1>, I get the following error:

Error found by spectre during envelope following analysis `envlp'.
ERROR: Can not find output signal 'my_net\<1\>' for fast envlp analysis, make sure 'output' parameter is correct'

So it looks like the translator is 'escaping' the bracket with a back slash and this is not interpreted correctly.

Any hints or suggestions on how to preserve bus notation? It produces far more readable schematics than having to explode each bus into its components.

Thanks,

Michele

  • Cancel
Parents
  • Tawna
    Tawna over 9 years ago
    Hi Michele, please file a Case with Customer Support http://support.cadence.com . We likely need to file a CCR for this.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Tawna
    Tawna over 9 years ago
    Hi Michele, please file a Case with Customer Support http://support.cadence.com . We likely need to file a CCR for this.
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information