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Phase noise simulation of PFD

praveenmv

I tried doing the phase noise simulation of a PFD using Pnoise analysis. I set the two inputs to the PFD (reference and feedback) at some phase offset and tried to find the phase noise for the output signal (defined as up-down). I observed that the simulated output phase noise varies inversely to the phase offset between two inputs. This is not expected as explained in http://www.designers-guide.org/analysis/PLLnoise+jitter.pdf . Please clear my doubt.

  • Hi Praveenmv,

    In steady-state loop operation, the loop will tend to drive the phase offset between the reference and feedback clock to zero (not withstanding static phase offset). Hence, of interest, is the variation in the gain of the PFD which will be a contributor to closed loop output phase noise. I am wondering if you are not simulating the phase noise of the gain - but rather the noise only of the voltage difference?

    You may be interested in the simulation methodology and discussion presented in the IEEE ICAS March 2013 journal article "Analysis of Phase Noise in Phase/Frequency Detectors". The noise component leading to phase noise at a frequency synthesizer's output clock is defined as the variation in the edges of the UP and DOWN outputs - not in the difference between the two voltages. Further, the UP and DOWN PFD outputs typically feed a charge pump if you are designing a PFD for use in a charge-pump based synthesizer.  Perhaps you can provide some added insight on your overall objective.

    Shawn

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