Inductor value and its Q factor

How can I measure value of an inductor and its Q value from its layout in virtuoso.

And how will that inductor be calculated ? will it be using some EM solver ? or will it be a parasitic extraction?

In our organization, we use the extracted view of the layout to simulate inductor Q using both spectre and a 2 1/2 D solver. The extracted view includes inductive components of the desired inductor as well as any neighboring paths. It is often necessary to include other parts of the circuit confusing the inductor in case they contain traces whose inductance is significant.

Dear engrvip,

> do u generate this extracted view using Quantus QRC

We actually use an extractor from another vendor.

> and what is this 2.5-D solver ? Is it different from EM solvers.

We use EMX to provide 3D simulations of the Virtuoso layout directly to determine the inductance and Q as a function of frequency. A model is fitted to the impedance which is substituted for the relevant area of the extracted view. The inductance/impedance of other traces neighboring the basic model are included in the extracted view.

Information on EMX, if you need it, may be found at URL:

I hope this helps understand out process.

Shawn

Hi Shawn  

What I understood is that virtuoso platform is used only for doing layout and rest of stuff like extraction and simulation (using field solver) is done external to virtuoso.

If I am right can I know why such approach , is cadence RF flow not capable to handle extraction and simulation of inductors ? How can I do complete inductor layout,extraction and simulation in cadence flow.

Vipul

There's an interesting paper by NXP from the CDN Live EMEA conference in 2012 which talks about using QRC for doing this extraction and comparing it with using an EM solver.

Cadence doesn't (these days) have an EM solver for IC use; there are various companies in our connections program who provide such tools though. As the paper linked to above suggests though, you might need to use a separate EM solver - it depends.

Regards,

Andrew

You might also want to take a look at http://www.designers-guide.org/Forum/YaBB.pl?num=1095265293 and http://www.designers-guide.org/Forum/YaBB.pl?num=1391077213.

Just one additional remark regarding the NXP presentation: If you use the Ladder Network, the size of the extracted netlist will grow a lot, so it is probably only practical for pretty small layouts.