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FM Demodulator, veriloga model simulation.

Alli

Hi,

I was trying to use the FM demodulate block from ahdlLib library which is integrated in the software. However after setting the parameters and running the simulation I get the following error:

Error found by spectre in `fm_demodulator', during circuit read-in.
ERROR (SFE-23): "/opt/cadence/IC617/tools/dfII/samples/artist/ahdlLib/fm_demodulator/veriloga/veriloga.va" 61: The instance `Pll' is referencing an undefined model or subcircuit, `pll'. Either include the file containing the definition of `pll', or define `pll' before running the simulation.

I was wondering how can I solve this issue?

 (I'm using: Version 14.1.0.921.isr17 64bit & MMSIM 141)

Thank you,

Parents

  • My guess is that you've put "veriloga" in the stop list. You're either using a config view (created with the hierarchy editor) and have set the stop list there to include "veriloga" (or you have set it as a stop point explicitly), or you're using a schematic as the top level and have changed Setup->Environment and added veriloga in the stop list.

    If I do that, I can reproduce the error you're getting - this would stop it expanding the hierarchy within fm_demodulator and doing the necessary steps to include the definition of pll into the netlist. You should not set veriloga to be a stop view.

    If it's not that, can you either share a screenshot of the hierarchy editor with the settings you're using, or the settings in Setup->Environment if not using a config view.

    Regards,

    Andrew.

Reply

  • My guess is that you've put "veriloga" in the stop list. You're either using a config view (created with the hierarchy editor) and have set the stop list there to include "veriloga" (or you have set it as a stop point explicitly), or you're using a schematic as the top level and have changed Setup->Environment and added veriloga in the stop list.

    If I do that, I can reproduce the error you're getting - this would stop it expanding the hierarchy within fm_demodulator and doing the necessary steps to include the definition of pll into the netlist. You should not set veriloga to be a stop view.

    If it's not that, can you either share a screenshot of the hierarchy editor with the settings you're using, or the settings in Setup->Environment if not using a config view.

    Regards,

    Andrew.

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