Hi,

From measurements we got a hint that the duty cycles of two clock signals change independently over time. We assume that this is a 1/f-noise effect and thus, I'm looking for a possibility to simulate the dynamic fluctuation (due to device noise) of clock duty cycles between two clocks which are 90-degree shifted.

Due to circuit architecture I already assume that from a certain starting point the noise introduced is not correlated between the two clock pathes due to separate buffer circuits and that I can simulate duty cycle variation for only one clock path and assume the delta in duty cycle between the two pathes is 3dB larger.

I tried PSS & PNOISE analysis with Noise Type set to "Jitter" and Crossing Direction to "all" in the PNOISE form. But I wonder if this method can be used to simulate the flutuation of the clock's duty cycle.

Looking at the spectre log file it seems to me that pnoise varies the clock edges independently for the rising and falling edges. So, I doubt if I can calculate the "duty cycle jitter" with this method.

I know that an alternative approach would be to do a transient noise simulation and plot the duty cycle for each cycle. But since my clock is above 2GHz and I'm looking for fluctuations happening in >100ms this would really be a long-running simulation.

Any hint on how to tackle this investigation would be helpful.

Best regards.