RF frequency synthesis problem- how low power?

I'm an undergrad working on the analog frontend for a student-developed cube satellite. After looking at the options, I've decided to use the CML Microcircuits CMX994 for the receiver and the CMX998 for the transmitter.

I chose the 994 for the RX because it's a direct conversion receiver, so I don't have to worry about external crystal or SAW filters for selectivity (they're kind of hard to find in small quantity for the frequencies I'd be interested in). Power consumption based on the datasheet seems reasonable, at less than 200 mW in low power mode. I chose the 998 for the TX for similar reasons - it does closed-loop predistortion to linearize the PA I designed, saving me from doing my own complicated digital predistortion setup.

I now need to decide how I'm going to do frequency synthesis. The 994 has an onboard frequency synthesizer, the 998 does not. The 994 has a buffer output to feed the 998, but that only works for half-duplex systems - I'm doing a full duplex setup (435 MHz RX, 144 MHz TX), so I need a separate frequency synth for the TX.

I'm not super concerned about the efficiency of the TX LO. When transmitting I'm pumping about 3.6 watts into the power amplifier (according to my ADS sims it'll be about 2W output at ~55% PAE). So, if I use a clock gen chip like the LMX2571 the added power consumption (100mW) next to the PA is pretty much negligible.

I'm more concerned about power efficiency for the RX LO, which will be running all the time. My options for generating the RX LO are:

1. Use the 994's onboard PLL and design a tank circuit for its VCO. This should take about 70 mW or so.
2. Use an off-the shelf low-power frequency synth with an integrated VCO like the LMX2571 (http://www.kynix.com/Parts/17564/LMX2571NJKR.html) from TI. This would take about 100 mW, but I avoid having to design a varactor-tuned tank circuit for the 994's VCO and potentially get a cleaner clock.
3. Use a PLL without an external VCO and design a low-power VCO from scratch. There are some seriously low power RF PLLs out there, but naturally they don't include the VCO.

So my question is basically this: if I sink 2-3 days into designing a very narrowband VCO, can I reasonably expect enough power efficiency improvement to make option #3 better than option #1? My frequency requirements for the VCO are pretty loose, I only need about a 20 MHz tuning range centered at 870 MHz.

I figure if I can cut LO consumption for the receiver to 50 mW or less, it'll be worth my time. As the LO buffer amp for the 994 takes 5mA when using an external clock, this means that the PLL + VCO together should consume less than about 30 mW - ie: 9 mA consumption at 3.3V, or less.

Given that I have only an undergrad level education (I'll be graduating in a few months), and access to design tools such as ADS and Genesys, is this something I could reasonably do, or should I focus my attention elsewhere?

Thanks for your help!