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  3. VCO verilogA model not running PSS

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VCO verilogA model not running PSS

NikosNaskas
NikosNaskas over 6 years ago

Dear all, 

I have a verilogA model of a VCO implemented as such:

_________________________________________________________________________________


`include "disciplines.vams"
`include "constants.vams"

//
// Voltage controlled oscillator with no jitter
//

module vco1 (out, in);

input in; voltage in; // input terminal
output out; voltage out; // output terminal
parameter real vmin=0; // input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf); // input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf); // minimum output frequency
parameter real fmax=2*fmin from (fmin:inf); // maximum output frequency
parameter real tt=0.01/fmax from (0:inf); // output transition time
parameter real ttol=1u/fmax from (0:1/fmax); // time tolerance
parameter real ampl=0.5 from (0:inf);
real freq, phase;
integer n;

analog begin
// compute the freq from the input voltage
freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

// bound the frequency (this is optional)
if (freq > fmax) freq = fmax;
if (freq < fmin) freq = fmin;

// bound the time step to assure no cycles are skipped
$bound_step(0.2/freq);

// phase is the integral of the freq modulo 2pi
phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

// generate the output
V(out) <+ ampl*cos(phase);
end

endmodule

_________________________________________________________________________________

I am trying to run a PSS analysis on a PLL consisting of the above VCO, a real PFD design and a simple 1st order filter made up of analogLib components. While a transient analysis

is able to finish without any issues or warnings a PSS analysis will not converge. Specifically I can see from the transient that the PLL has locked within about 30ns. PSS analysis detects steady state

at 33ns but  fails at arround 32ns-33ns. I have simulated the PLL using transient for up to 150ns and it is perfectly stable. I have tried numerous options on the PSS but without getting any results. I have tried to force the

PSS to run a very long transient simulation to ensure the PLL has stabilized but still no luck. I specifically get the following errors:

____________________________________

==============================
`pss': time = (32 ns -> 33 ns)
==============================
Zero diagonal found in Jacobian at `net028' and `net028'.
Zero diagonal found in Jacobian at `net028' and `net028'.
Zero diagonal found in Jacobian at `net028' and `net028'.
Zero diagonal found in Jacobian at `net028' and `net028'.
Jacobian was reordered during integration. Don't use swap file in PSS analysis
Zero diagonal found in Jacobian at `net028' and `net028'.
pss: time = 32.03 ns (2.54 %), step = 441.1 fs (44.1 m%)
pss: time = 32.08 ns (7.56 %), step = 779.7 fs (78 m%)
pss: time = 32.13 ns (12.5 %), step = 846.5 fs (84.6 m%)
pss: time = 32.18 ns (17.6 %), step = 554.7 fs (55.5 m%)
pss: time = 32.23 ns (22.6 %), step = 2.632 ps (263 m%)
pss: time = 32.28 ns (27.6 %), step = 2.632 ps (263 m%)
pss: time = 32.33 ns (32.6 %), step = 2.632 ps (263 m%)
pss: time = 32.38 ns (37.6 %), step = 2.632 ps (263 m%)
pss: time = 32.43 ns (42.5 %), step = 511.1 fs (51.1 m%)
pss: time = 32.48 ns (47.6 %), step = 2.632 ps (263 m%)
pss: time = 32.53 ns (52.5 %), step = 406.3 fs (40.6 m%)
pss: time = 32.58 ns (57.5 %), step = 1.154 ps (115 m%)
pss: time = 32.63 ns (62.5 %), step = 454.9 fs (45.5 m%)
pss: time = 32.68 ns (67.6 %), step = 2.632 ps (263 m%)
pss: time = 32.73 ns (72.6 %), step = 2.632 ps (263 m%)
pss: time = 32.78 ns (77.6 %), step = 2.632 ps (263 m%)
pss: time = 32.83 ns (82.6 %), step = 2.632 ps (263 m%)
pss: time = 32.88 ns (87.5 %), step = 371.3 fs (37.1 m%)
pss: time = 32.93 ns (92.7 %), step = 2.632 ps (263 m%)
pss: time = 32.98 ns (97.7 %), step = 2.632 ps (263 m%)
Conv norm = 14.3e+06, max dV(net024) = 36.5826 kV, took 1.43 s.


==============================
`pss': time = (32 ns -> 33 ns)
==============================

Error found by spectre at time = 32.08 ns during periodic steady state analysis `pss'.
ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. Last acceptable solution computed at 32 ns.

The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol

Top 10 Residue too large Convergence failure:
V(I62.I57.I60.net7) = -3.16705 V, previously -3.16705 V.
residue too large: | 39.6793e+114 A | > 396.793e+108 A + 100 fA
V(I62.I58.I80.net7) = -1.5006 V, previously -1.5006 V.
residue too large: | 1.83385e+117 A | > 18.3385e+111 A + 100 fA
V(I62.I58.I60.net7) = -8.61477 V, previously -8.61477 V.
residue too large: | 19.8331e+114 A | > 198.331e+108 A + 100 fA
V(I62.I58.net1) = 1.00293 V, previously 1.00293 V.
residue too large: | -36.036e+24 A | > 360.36e+18 A + 100 fA
V(I62.I58.CLK_i) = 5.58113 V, previously 5.58113 V.
residue too large: | -733.948e+15 A | > 7.33948 TA + 100 fA
V(I62.net020) = -27.3343 V, previously -27.3343 V.
residue too large: | 4.28083e+108 A | > 42.8083e+102 A + 100 fA
V(UP) = -682.489 mV, previously -682.489 mV.
residue too large: | 40.4116e+108 A | > 404.116e+102 A + 100 fA
V(I62.I58.B) = -12.6532 V, previously -12.6532 V.
residue too large: | 74.695e+117 A | > 746.95e+111 A + 100 fA
V(I62.I58.net019) = -11.1717 V, previously -11.1717 V.
residue too large: | 11.3806e+15 A | > 113.806 GA + 100 fA
V(I62.net037) = 384.159 V, previously 384.159 V.
residue too large: | -339.142e+117 A | > 3.39142e+114 A + 100 fA

_______________________________________________________________

Any input is highly appreciated.

Thanks 

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  • ShawnLogan
    ShawnLogan over 6 years ago

    Dear  NikosNaskas,


    The value of Conv norm suggests the steady-state solution PSS finds is far from periodic. This will result in a steady-state solution failure. Is a time of 32 ns or 33 ns really sufficient for your circuit to reach its steady-state? If not, I would recommend that you include a value of tstab that places the response much closer to its steady-state solution.

    Some information on the value of Conv norm spectre uses to define an acceptable steady-state solution is provided in the Sourcelink document

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000sg3UEAQ&pageName=ArticleContent

    I hope this helps NikosNaskas,

    Shawn

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  • ShawnLogan
    ShawnLogan over 6 years ago

    Dear  NikosNaskas,


    The value of Conv norm suggests the steady-state solution PSS finds is far from periodic. This will result in a steady-state solution failure. Is a time of 32 ns or 33 ns really sufficient for your circuit to reach its steady-state? If not, I would recommend that you include a value of tstab that places the response much closer to its steady-state solution.

    Some information on the value of Conv norm spectre uses to define an acceptable steady-state solution is provided in the Sourcelink document

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000sg3UEAQ&pageName=ArticleContent

    I hope this helps NikosNaskas,

    Shawn

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to ShawnLogan

    In addition to Shawn's advice, you've not given a great deal of info either - the model itself seems OK (I can run PSS in oscillator mode on this and it works OK - although the bound step is a bit big by default - only 5 points per period is a bit small).

    How are you running PSS? If it's for the whole PLL, then this should be defined as a driven circuit (i.e. don't define it as an oscillator, because the output of the PLL is a harmonic of the input frequency when locked - this is assuming that your divider is an integer division).

    Without more info on the PLL itself, it's hard to tell you what the problem is. Since it's made of ideal components, can you provide the entire circuit (the input.scs) and all models you're using?

    Regards,

    Andrew.

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