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amplifier Assura LVS check problem

yefJ

Hello , i have built an aplifier in schematics which worked fine, when i tried to  convert my schematics into layout , when i tried Assura LVS check,i get an error as shown bellow.

I have attached the full LOG.

Where did i go wring with the LVS rule file?

Thanks.

Fullscreen 0728.log.txt Download 
 Assura (R) Physical Verification Version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.4
            Release 4.1_USR5_HF10

Copyright (c) Cadence Design Systems. All rights reserved.
@(#)$CDS: assura_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.4 05/18/2017 07:53 (sjfnl667) $
sub-version 4.1_USR5_HF10, integ signature 2017-05-18-0730

run on micron.eng.tau.ac.il from /eda_disk/cadence/tools/ASSURA/617a/tools.lnx86/assura/bin/64bit/assura on Wed Apr 10 19:56:19 2019


Starting /eda_disk/cadence/tools/ASSURA/617a//tools.lnx86/assura/bin/aveng /projects/VLSI_labs/RFIC/yafimv/RF_090/afterK/amplifier.rsf -exec1 -LVS -cdslib /projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib
@(#)$CDS: aveng_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.4 05/18/2017 07:53 (sjfnl667) $
sub-version 4.1_USR5_HF10, integ signature 2017-05-18-0730

run on micron.eng.tau.ac.il from /eda_disk/cadence/tools/ASSURA/617a/tools.lnx86/assura/bin/64bit/aveng on Wed Apr 10 19:56:19 2019

 Summary Report: amplifier.sum
 RSF           : /projects/VLSI_labs/RFIC/yafimv/RF_090/afterK/amplifier.rsf
 Library Name  : afterK
 CDSLIB Path   : "/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib"
 Cell Name     : amplifier
 View Name     : layout
 Rules File    : /home/pdks/UMC/UMC90nm/RuleDecks/Assura/LVS/G-DF-LOGIC_MIXED_MODE90N-1P9M-LOW_K_ASSURA-LVS-1.2-P5-EXTRACT.RUL
 Options       : -exec1 -LVS -cdslib /projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib 
 Work Directory: /projects/VLSI_labs/RFIC/yafimv/RF_090/afterK
 Operating Mode: Legacy Mode is Off


Starting dfIIToVdb...
Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.01s.
@(#)$CDS: dfIIToVdb_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.4 05/18/2017 07:58 (sjfnl667) $
sub-version 4.1_USR5_HF10, integ signature 2017-05-18-0730

run on micron.eng.tau.ac.il from /eda_disk/cadence/tools/ASSURA/617a/tools.lnx86/assura/bin/64bit/dfIIToVdb on Wed Apr 10 19:56:19 2019

*WARNING* The directory: '/projects/VLSI_labs/RFIC/shayavne/RF_090/shay' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'shay'.
*WARNING* The directory: '/data.cc/data/a/home/cc/students/enginer/yafimv/RF_090/rf_090' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'rf_090'.
*WARNING* The directory: '/eda_disk/agilent/ADS2017/GoldenGate_474/aa/615/goldenGateLib' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'goldenGateLib'.
*WARNING* The directory: '/eda_disk/agilent/ADS2017/cdslibs/6.1.0/adsLib' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'adsLib'.
*WARNING* The directory: '/projects/VLSI_labs/RFIC/shayavne/RF_090/shay' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'shay'.
*WARNING* The directory: '/data.cc/data/a/home/cc/students/enginer/yafimv/RF_090/rf_090' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'rf_090'.
*WARNING* The directory: '/eda_disk/agilent/ADS2017/GoldenGate_474/aa/615/goldenGateLib' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'goldenGateLib'.
*WARNING* The directory: '/eda_disk/agilent/ADS2017/cdslibs/6.1.0/adsLib' does not exist
	but was defined in libFile '/projects/VLSI_labs/RFIC/yafimv/RF_090/cds.lib' for Lib 'adsLib'.
Loading umc90nm/libInit.il ...
	Loading umc90nm/loadCxt.ile ... done!
	Loading context 'forInd' from library 'umc90nm' ... done!
	Loading context 'Util' from library 'umc90nm' ... done!
	Loading context 'umc90nm' from library 'umc90nm' ... done!
	Loading context 'pdkUtils' from library 'umc90nm' ... done!
	Loading context 'RF_CB_all' from library 'umc90nm' ... done!
	Loading context 'pcellUtil' from library 'umc90nm' ... done!
	Loading context 'MM_other_CB' from library 'umc90nm' ... done!
	Loading context 'oxf_cb' from library 'umc90nm' ... done!
	Loading umc90nm/.cdsenv ... done!
	Loading umc90nm/libInitCustomExit.il ... done!
Loaded umc90nm/libInit.il successfully!
Compiling rules...


************************************************************* 

 Assura LVS of UMC 90nm 1P9M Logic/Mixed Mode LOW-K Process (Ps: Pls select the switches of metal opton and metal combination !! )  
  
  
 

************************************************************* 

ERROR (AVRC-10132): Unknown layer 'CRTOP' used in statement 'geomAnd()'.
 Layer must be defined before its usage.
  Either statement or layer name must be corrected.
   641. geomAnd(CRTOP LLMARK)
Errors exist in the rules file '/home/pdks/UMC/UMC90nm/RuleDecks/Assura/LVS/G-DF-LOGIC_MIXED_MODE90N-1P9M-LOW_K_ASSURA-LVS-1.2-P5-EXTRACT.RUL'.


*****  dfIIToVdb terminated abnormally  *****

*WARNING* Translation abnormally terminated!


*****  aveng fork terminated abnormally  *****


*WARNING* aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated

  • It's quite hard to help without being able to see the rule file, but the error message is fairly clear:

    *************************************************************

    Assura LVS of UMC 90nm 1P9M Logic/Mixed Mode LOW-K Process (Ps: Pls select the switches of metal opton and metal combination !! )

    *************************************************************

    ERROR (AVRC-10132): Unknown layer 'CRTOP' used in statement 'geomAnd()'.
    Layer must be defined before its usage.
    Either statement or layer name must be corrected.
    641. geomAnd(CRTOP LLMARK)
    Errors exist in the rules file '/home/pdks/UMC/UMC90nm/RuleDecks/Assura/LVS/G-DF-LOGIC_MIXED_MODE90N-1P9M-LOW_K_ASSURA-LVS-1.2-P5-EXTRACT.RUL'.

    Perhaps you need to pick an appropriate switch for the metal option/combination as the message says? I don't know what they are, but maybe the documentation for the PDK/rule deck explains this? I suspect that without the correct switches, it doesn't set up the input layers properly and hence the later part of the rule file fails.

    Regards,

    Andrew.

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