ideal op amp comparator settings

I'm not sure why it would have a 0.8V steady output from the description you've given - maybe showing the netlist would help? However, it's certainly not going to work properly - feeding a 1ns period pulse into an opamp with 8MHz unity-gain bandwidth is really not going to work well (or 8MV/s slew rate).

Here's how it works with the configuration you've given but a slower frequency pulse. With the period you gave it had a slowly ramping signal as the slew rate and bandwidth of the amp would limit its ability to respond:

Regards,

Andrew.

Hello Andrew, As shown in your example too,Why does the OPAMP (in the /op node)  switches between 0.3V and 0.85V?

Its suppose to go from 1.2 till 0.

Thanks

Dear yefj,

yefJ said:

As shown in your example too,Why does the OPAMP (in the /op node)  switches between 0.3V and 0.85V?

Its suppose to go from 1.2 till 0.

Di you examine the verilogA code yefj? There is a soft limiting parameter whose default value is 0.50 V. From your description, you did not set the soft limiting value and hence, as shown in the attached verilogA code, it is set to 0.50 V. Note that in Andrew's simulation data, the opamp output voltage swings between 350 mV and 850 mV. These voltage values are about 350 mV above the minimum supply of 0 V and 350 mV below the maximum supply of 1.20 V. Hence, it suggests the limiting voltages are symmetric from the upper and lower suppy voltages and due to the soft limiting default value that you did not change. The verilogA file from the Cadence install directory is attached. 

Shawn

`include "discipline.h"
`include "constants.h"

// $Date: 1997/08/28 05:45:21 $
// $Revision: 1.1 $
//
//
// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//

`define PI 3.14159265358979323846264338327950288419716939937511

//--------------------
// opamp
//
// - operational amplifier
//
// vin_p,vin_n: differential input voltage [V,A]
// vout: output voltage [V,A]
// vref: reference voltage [V,A]
// vspply_p: positive supply voltage [V,A]
// vspply_n: negative supply voltage [V,A]
//
// INSTANCE parameters
// gain = gain []
// freq_unitygain = unity gain frequency [Hz]
// rin = input resistance [Ohms]
// vin_offset = input offset voltage referred to negative [V]
// ibias = input current [A]
// iin_max = maximum current [A]
// slew_rate = slew rate [A/F]
// rout = output resistance [Ohms]
// vsoft = soft output limiting value [V]
//
// MODEL parameters
// {none}
//

module opamp(vout, vref, vin_p, vin_n, vspply_p, vspply_n);
input vref, vspply_p, vspply_n;
inout vout, vin_p, vin_n;
electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n;
parameter real gain = 835e3;
parameter real freq_unitygain = 1.0e6;
parameter real rin = 1e6;
parameter real vin_offset = 0.0;
parameter real ibias = 0.0;
parameter real iin_max = 100e-6;
parameter real slew_rate = 0.5e6;
parameter real rout = 80;
parameter real vsoft = 0.5;
real c1;
real gm_nom;
real r1;
real vmax_in;
real vin_val;

electrical cout;

analog begin

@ ( initial_step or initial_step("dc") ) begin
c1 = iin_max/(slew_rate);
gm_nom = 2 * `PI * freq_unitygain * c1;
r1 = gain/gm_nom;
vmax_in = iin_max/gm_nom;
end

vin_val = V(vin_p,vin_n) + vin_offset;

//
// Input stage.
//
I(vin_p, vin_n) <+ (V(vin_p, vin_n) + vin_offset)/ rin;
I(vref, vin_p) <+ ibias;
I(vref, vin_n) <+ ibias;

//
// GM stage with slewing
//
I(vref, cout) <+ V(vref, cout)/100e6;

if (vin_val > vmax_in)
I(vref, cout) <+ iin_max;
else if (vin_val < -vmax_in)
I(vref, cout) <+ -iin_max;
else
I(vref, cout) <+ gm_nom*vin_val ;

//
// Dominant Pole.
//
I(cout, vref) <+ ddt(c1*V(cout, vref));
I(cout, vref) <+ V(cout, vref)/r1;

//
// Output Stage.
//
I(vref, vout) <+ V(cout, vref)/rout;
I(vout, vref) <+ V(vout, vref)/rout;

//
// Soft Output Limiting.
//
if (V(vout) > (V(vspply_p) - vsoft))
I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft);
else if (V(vout) < (V(vspply_n) + vsoft))
I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft);
end
endmodule

Hello Shawn , so in order to overcome this limitation and make it switch from 0 to 1.2  we need to set vsoft=10 instead of vsoft=0.5?

parameter real vsoft = 10;

Thanks

Why would you set it (vsoft) to 10V below the supply rails? That's clearly not going to work (clear if you read the model).

In fact, why don't you just use a comparator model (there's one in ahdlLib and also one at https://designers-guide.org/verilog-ams/index.html ) rather than trying to use a general opamp model that you don't understand?

Regards,

Andrew.

Dear yefj,

Please consider using the comparator model as Andrew suggests.  I also agree 100% with Andrew that it does not make any sense to set vsoft to 10 if you want the opamp voltage swing to approach 0 and 1.2 V ( the ground and supply potentials). It appears you may not understand what vsoft is and using the opamp model to accomplish your goal is confusing you.

Thank you, Andrew, for your suggestion to yefj!

Shawn

Hello Andrew, Thank you very much  for the LINK , i managed to write and simulate the OPAMP i needed  as shown bellow.

One thing that intrests me is the interaction between "verilog component" and "REAL" netlist component.

Regarding Impedance what output impedance my OPAMP will present to the surrounding real components?
Thanks 

The output impedance is 0 because you didn't model any output impedance - it's an ideal voltage source.

Andrew.