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Phase Noise Analysis on a Gated Ring Oscillator

bvanbockel

I am designing a Gated Ring Oscillator (GRO), To be used in a Time to Digital Converter (TDC).
To get an idea about the performance of the GRO, I would like to perform a phase noise analysis.

I already did some phase noise measurements using PSS and PNOISE from a regular ring oscillator, this work fine.
The challenge with the GRO is that the free running ring oscillator (1.127 GHz) is only enabled for a small period in time, this at a frequency of a the input reference clock (50MHz)

Running the PSS simulation on this circuit always ends up not able to converge. Is there someone that already performed phase noise measurements on a GRO?

  • Dear bvanbockel,

    Is there a reason you cannot operate the ring VCO in its enabled state and use that data? I am trying to think of a mechanism where the phase noise will be different on a transient basis from its steady-state value and nothing is coming to mind. There will, of course, be some frequency drift relative to its steady-state frequency, but I don't think that will effect phase noise at any relevant offset frequencies. There will also be a start-up and power-down transient. However, that neither of those appears to impact phase noise as the phase noise is only defined about some carrier frequency and not a frequency "chirp". Perhaps it might help me understand (anyway) why you believe a pss simulation of the gated VCO is necessary in its gated mode of operation. In other words, what exactly are you trying to quantify about your TDC?

    Sorry I can not think of any better response!

    Shawn

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