cadence gpdk45 off grid problem

There appears to be a small jog in the poly and metal routing connecting to the nmos transistor at the bottom which I suspect is related to the problem. Using the Edit Properties form look at the attributes for the selected nmos to check the x and y to see if that's on grid.

To be honest, the first thing I'd do is see where the off grid errors are - the Assura UI will highlight them - otherwise this is just guesswork from a picture. By the way, the numbers before each error line are not the layer numbers, but the number of violations.

Regards,

Andrew.

Hello Andrew , i have connected the source of the pmos to the NWell  and the source of the nmos to Psub using M1 vias.

It says the my Nwell is floating,but i clearly connected  both the Nwell and Psub with metal1 as shown bellow, its not floating.

where did i go wrong?

Thanks

Presumably your off-grid errors are resolved? Thanks for confirming that...

The issue is that the well on the pmos transistor is floating. You have not connected it. The metal on the source (or drain) of the pmos transistor only connects to the source or drain - not to the well. You have added a second well around the well contact at the top, but that's separate from the well for the transistor; the metals connecting to the top well contacting is connected to the source/drain of the transistor, but nothing connects it to the well of the transistor. The wells need to be connected for this to be actually connected, and they are not.

So your nwell shapes need to join between the pmos transistor and the nwell contact.

Andrew.

Hello Andrew , yes the off grid issue was solved after i made the M1 connection wider to fit the whole via .
Regarding the floating Well of the PMOS and nmos. is it the area sighned in red arrow shown in a photo bellow?

its too small to put a VIA  connection as shown bellow inside this small area .

How can i see the area of the PMOS Nwell?

Thanks

How can 

Hello Andrew , yes the off grid issue was solved after i made the M1 connection wider to fit the whole via .
Regarding the floating Well of the PMOS and nmos. is it the area sighned in red arrow shown in a photo bellow?

its too small to put a VIA  connection as shown bellow inside this small area .

How can i see the area of the PMOS Nwell?

Thanks

How can 

yefJ said:

How can i see the area of the PMOS Nwell?

By looking at the Nwell rectangle where the PMOS device is? There's a purple box on the layer Nwell over the transistor - either zoom in or make just Nwell visible - it's quite easy to see.

Draw a rectangle on Nwell joining the Nwell of your well contact to the Nwell of the transistor - then you will have a single well containing both the well contact (which will connect the well to the metal) and the well which forms the bulk of the pmos transistor.

Andrew.

Hello Andrew, i managed to solve this issue as you said ,but NMOS and PMOS look identical  , and they suppose to differ as shown in the left layout.

They suppose to differ  by the Well layer that is suppose to be present on PMOS only .

i assume that its eigther we have PWELL on the NMOS too , or the NWELL is not visible.

which one is our case?

Thanks

What are you on about? Even I can see the purple rectangle in the small picture you are showing, and the pmos device looks nothing like the nmos device. The picture you're showing (presumably from some academic text) is showing the diffusion for a pmos and nmos in different colours, but it's far more conventional to have a region of N or P implant instead over a common diffusion (called "Oxide" in gpdk045 - the name varies from technology to technology). 

If you'd either controlled the layer visibility using the layer palette (as I suggested) or used Window->Assistants->Dynamic Selection and move your cursor over the pmos or nmos transistor, you'll see the layers that make up the device. You can even freeze the layers shown in the Dynamic Selection assistant using control-H (control-H again to unfreeze). You can then select the rows in the dynamic selection assistant (when frozen) to highlight the P-implant and N-Well shapes.

The nmos device has an N-implant and a pseudo-pwell (called PWdummy). There's no actual pwell in this technology - it's just used for connectivity tracing reasons and so is a pseudo layer (it's quite common for a p-substrate process to only have nwell and no pwell).

Andrew

Hello Andrew , following your instructions i have made a layer view like you said on the source side and compared  the theoretical  layers with the  on "source" of each transistor at  gpdk45 nmos source.(as shown bellow)

on NMOS top to bottom order in theory we see: metal->n+ diffusion->psub

In reality i see at Nmos top  to bottom  order we see: pwdummy->metal1->two layers of Nimp 4,5->oxide->metal.

on PMOS we have in theory top to bottom: metal1->P+ diffusion->nwell->Psub
In reality as shown bellow we have: metal1->two layers of Ptype  implant(3,4) ->nwell->oxide 

Its not the same thing at Nmos as shown in the photo bellow we are not suppose to have metal on the bottom or oxide on the buttom(the dummy element i suppose has no effect)

PMOS resembles theory more, where did i go wrong in the differences i see regarding the theory and reality of the NMOS gpdk45?

Thanks

The order in the dynamic selection is not the vertical order of the layers in the process from top to bottom or bottom to top. It's far more arbitrary than that - it is certainly not intended to give any indication of physical stack order. The fact that there are multiple shapes is just because you have rules which require the implant to extend over the gate extension (I think) in this process. 

The metal (marked 7) in the NMOS is the top level interconnect shape and not part of the transistor.

Essentially you are reading too much meaning into the order you see in the dynamic selection assistant. I don't know why you did that, because nothing gives any indication it should be treated as the layer stack order.

Hello Andrew, Yes i understood the view of the layers.

When i try to double click the error its supposed to show me the area where the error accurs,but by switching from one error to another it doesnt show at all.

Maybe its because of the type of the error? for example the width of the NWELL is not some thing i can control, its thePDK technology.  gpdk45 Nmos device was made that way.

How can i increase the nwell of the transistor?  There is only Lenght(45nm) and Width i can play with .

Thanks

When you select another error, use the right arrow in the UI to visit each of the errors. The pair of left/right errors next to the AV/NV buttons visit the next error on the current rule. The left/right arrows to the right of the Cell Filter visit the next/previous error in the current cell (the tooltips over the arrows tell you this). Just clicking on the next error line doesn't show you where they are - you need to visit each. So it's nothing to do with the error being in the transistor - just that you're probably not actually hitting the correct button...

If you have a minimum size device, the height of the nwell on the pmos at the top will be too narrow and less than the minimum width. There is nothing to stop you drawing a rectangle of nwell over the transistor which is greater than 0.3um wide (or high) so that you meet that rule. Each device does not guarantee to meet all the design rules in isolation - if the pcell draw an nwell shape larger than needed for the overlaps, it would limit you because if the additional nwell needed to meet the rule was above or below the transistor, it might not be where you want - whereas if you can draw it yourself, you have more flexibility.

It's not that common to solely have a single minimum sized device in a well - usually you would share the well with other devices, and it's then easy to ensure that such minimum rules are met.

I really think you need to talk to your supervisor about all these questions because this forum cannot be a means to teach you how to do IC layout!

Regards,

Andrew.

Hello Andrew ,is there a document about the gpdk45 that talks about its DRC standards? 

so i could interpret those layer size errors.
i tried to search for one and couldnt find a document that actually describes each DRC rule and how it should look,it would be very helpfull.
Thanks .

This is in gpdk045 v5.0 :

UNIX> ls $KITHOME
assura/ diva/ gpdk045/ libManager.log pvs/ soce/
assura_tech.lib* docs/ gpdk045.tf models/ pvtech.lib*
cds.lib dumpit.cdf lib.defs pmos1v.cdf qrc/
UNIX> ls $KITHOME/docs
RELEASE_NOTES gpdk045_PDK_Model_Report.pdf gpdk045_pdk_referenceManual.pdf
VERSION gpdk045_drc.pdf

The gpdk045_drc.pdf is the document that describes the design rules - quite clearly.

Regards,

Andrew.

Hello Andrew, i tried to follow you direction.i get undefined variable problem as shown in the print screen bellow.
is there some link from the Cadence website i can use?
Anyway Thank you very much for the guidance.