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gpdk45 Gate source switch charge injection feedthrew

robert 21

Hello, I am trying to simulate a physical phenomena of charge injection from gate to source, as shown in the schematics bellow.

the principal says that when we switch voltage from VDD to 0 on the gate, although the charging has to stop there is still the curent flow from gate to sourse from the overlap parasitic capacitance.

I=C*dv/dt when voltage changes there is a current flow threw the capacitor.However when i tried to simulate this effect in cadence, i got  a very idial behavior.

I trying to change the Width of the NMOS  ,rise time fall time, it presents me an idial behavior.

Is there something i can do to see this effect in cadence virtuoso?
Thanks

FYI This is yefj , i had problem with my user and i was told by the cadence support to re-register :-) i will change my nick as soon as possible.

  • Dear yefj,

    robert 21 said:
    Is there something i can do to see this effect in cadence virtuoso?

    I believe the reason you are not seeing the impact of charge injection is that you have an ideal voltage source and ideal capacitor connected to the drain and source of your MOS transistor. As such, the impact of the charge transfer is not evident in the voltage at the drain or source of the MOS device.

    To see the impact, I would suggest one of the two options:

    1. Add a current probe in series with your ideal voltage source and a second in series with the ideal drain capacitor and save the current in each probe. Re-simulate your circuit and examine the current through each probe. If my hypothesis is correct, I think you will see the source and drain currents increase as charge is injected at each gate transition.

    2. Add some finite resistive impedance with your ideal drain and source voltage source and capacitor respectively and re-simulate. Plotting the drain and source voltages should reveal the charge injection as the injected charge produces a voltage transient across the finite resistances you added.

    I have attached a PowerPoint file with your initial circuit with added current probes. Page 1 is the test bench. Pages 2 and 3 include plots of the drain, source and gate voltages. Page 3 is an expanded view of page 2 and illustrates the impact of charge injection.

    I hope this helps.

    Shawn

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