Hello, I have an issue that my data falling edge is very close to the clock rising edge, thus logic '1' doesnt get sampled as you can see in the arrows in the last photoso i got to the conclution that altough we have VDD at the gate there has to pass some minimal time for the mosfet to create an invertion layet(channel)
is there a way to simulate and see this amount of time in cadence virtuoso?Thanks
robert 21 said:
...so i got to the conclution that altough we have VDD at the gate there has to pass some minimal time for the mosfet to create an invertion layet(channel)
is there a way to simulate and see this amount of time in cadence virtuoso?
In examining your schematic, I believe the issue is related to the topology of the circuit you present. I may not be observing the entire schematic or am overlooking something, but it appears your flip-flop is missing a transmission gate between your feedback inverter and node D_tg. As a result, your circuit is always trying to force the node D_tg to the complement of the output node "Q_not". Hence, the ability of the input node data to drive node D_tg is quite limited.
In a standard transmission gate DFF there are two transmission gates that open on opposite states of the CLK signal. When the input transmission gate is transparent, the feedback transmission gate (which is missing but I believe should be in series with your feedback inverter) is an open circuit to allow the input data source to charge node D_tg to the voltage on node "data". In the opposite clock state, the input transmission gate creates and open circuit and the feedback transmission gate becomes transparent to maintain the voltage on D_tg to its last value.
Let me know if my assessment of your intended circuit makes sense. There are ways to simulate the set-up/hold times of a DFF, but I think the circuit topology needs to be corrected first. I hope this helps Robert.
Hello Shawn, i have corrected my FF topology and made it exactly as in theory shown bellow.
Instead of making many printrscreen of the result i have exctracted GRF and attached file from cadence plot and compressed it so it could be uploaded to the post, So you could see the plots in each stage.I see that there is a sampling issue,you have mentioned technique for finding out the setup and hold time needed between clock and data.
How to simulate the basic time needed for the invertion tunnel to be created in a mosfet (Tsetup time) and thold time?Thanks
A .grf file does not contain any data. It only points to the data source. Hence, I am not able to view any of your waveforms. In any case, one measures the setup and hold times of, for example, a DFF by sweeping the input data across the sampling edge of the clock using a series of transient simulations and measuring the clock to Q propagation delay time at each simulation. A plot is created of the propagation delay as a function of this delay time. The delay times that correspond to an increase of 5% in the propagation delay time where the sampling time is more than sufficient defines the set-up and hold times. I have attached a couple of figures from a 2001 IEEE paper that illustrate the type of plot you will generate and the resulting definitions. The per cent increase may vary depending on the author and I have seen percent increases of between 1% and 10% in use. There is not much difference as the curve is quite steep over these regions. You will need to step the clock and data by very small time increments to characterize the propagation delay.
I hope this helps.
Hello Shawn i have three questions, in the plots bellow i made a mistake and named Q_not as Q but its works as in theory.
1.Why is its called edge triggered, its passing data when clock is Level 1 not on the clk transition between 0 and 1(as you can see in the plots bellow)
2.i need to make a reset input for this FF so my output will be zero when reset=1, how should i implement the reset function in the flip flop shown bellow
so i could use it as a phase detector later(i got to the conclution that beacuse its a clock system then we should feed the latch with zero for long enough time)?
3.Going to the original question of the Tsetup, the pass gate cannot sample the data if its gate voltage is not set for long enogh time,
how can i see this physical effect in cadence(how to see that the enough time passed for the mosfet channel has formed)
> 1.Why is its called edge triggered, its passing data when clock is Level 1 not> on the clk transition between 0 and 1(as you can see in the plots bellow)
Please refer to the attached file "roberts_annotated_waveforms_edge_triggered_sml_083119.png" that illustrates why the DFF is edge triggered and not level sensitive.
> 2.i need to make a reset input for this FF so my output will be zero when> reset=1, how should i implement the reset function in the flip flop shown> bellow
I believe this is a design related question. Although I can provide an answer, if you are a student, I think researching this will provide a more lasting learning experience. There are many references on this subject and many means of adding a reset function. If you have problems finding potential solutions, let me know and I will try to provide additional insight. Please think about your circuit and how a reset function might be included.
> 3.Going to the original question of the Tsetup, the pass gate cannot sample> the data if its gate voltage is not set for long enogh time> > how can i see this physical effect in cadence(how to see that the enough time> passed for the mosfet channel has formed)
The limiting factor is not how long it takes to form an inversion channel in the MOS device. The factor limiting the setup and hold times are the RC time constants of the transmission gates. The electric field required to form an inversion channel is extremely fast and limited by how long it takes the capacitances to charge and discharge to actually produce the required electric field.
I hope I understood your questions correctly.