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test signal iprobe rout calculation

robert 21

Hello , i am trying  to extract small signal Rout of a circuit with test source sweep.

For that i have defined and ac sweep of a test source on the output and to divide it by measured current in Iprobe.

i have done ac sweep for making   making other dc sources gnd leaving Vtest only active, as shown bellow.

However i got an   error as shown bellow,where i was wrong with my ac ,Vtest Iprobe method for finding rout?

Thanks.

"FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
V2:p (from net3 to 0)"

OP Rout Vds plot:

Fullscreen error2.txt Download 
The CPU load for active processors is :
        Spectre  0 (21.1 %)      1 (5.1 %)       2 (1.8 %)       3 (34.6 %)
                 4 (1.2 %)       6 (3.0 %)       7 (1.5 %)       9 (3.9 %)
        Other  

Time for Elaboration: CPU = 18.998 ms, elapsed = 47.0309 ms.
Time accumulated: CPU = 540.917 ms, elapsed = 3.43958 s.
Peak resident memory used = 69.4 Mbytes.


Time for EDB Visiting: CPU = 0 s, elapsed = 378.132 us.
Time accumulated: CPU = 540.917 ms, elapsed = 3.44007 s.
Peak resident memory used = 69.9 Mbytes.
Fatal error found by spectre during topology check.

    FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
        V2:p (from net3 to 0)


Aggregate audit (11:15:29 AM, Wed Nov 13, 2019):
Time used: CPU = 591 ms, elapsed = 6.03 s, util. = 9.8%.
Time spent in licensing: elapsed = 205 ms.
Peak memory used = 81.9 Mbytes.
Simulation started at: 11:15:23 AM, Wed Nov 13, 2019, ended at: 11:15:29 AM, Wed Nov 13, 2019, with elapsed time (wall clock): 6.03 s.
spectre completes with 1 error, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

  • (IPRB0 + V2) and V0 are in parallel. You cannot have two voltage sources in parallel (even if they're the same voltage) as it makes the circuit impossible to solve. The iprobe is effectively a zero-volt source, and so it means that you have competing values for the vdd net.

    Andrew.

  • in reply to Andrew Beckett

    Hello Andrew i have changed the Vtest source to be AC source only at 1k so the DC source will be GND inseat of some DC value.(as shown bellow),and it still gives me the same error.

    every small signal analysis uses this method to find rout.

    where did i go wrong in inplemeting this method of finding rout in cadence virtuoso?

    Thanks

  • in reply to robert 21

    There is no such thing as an AC-only source (in any simulator), and so for the DC analysis you have a 0V source in parallel with a 1.8V source, for which no solution is possible (since both sources are ideal, it can't be both). I have never seen anyone trying to measure rout this way (it cannot possibly work).

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Dear robert21,

    robert 21 said:
    every small signal analysis uses this method to find rout.

    Andrew is correct, robert21. Your test bench does not appear to be consistent the circuit topology used to determine output impedance of a three terminal device. Why? Consider what the impedance looks like as you look into the unlabeled node of the drain of the MOS device. Referring to Figure 1 below, the input impedance consists of the parallel impedances of your vdd source and the rout of the MOS device whose output impedance you are interested. Since the DC source vdd has zero impedance, the impedance shown as Zin will be zero. Your topology shunts the rout of the MOS device by the zero impedance of the voltage source vdd. I hope this makes sense robert21. Let me know if it does not.

    What is needed to measure rout with a test bench similar to yours is a series impedance in the vdd source that will not significantly impact the device rout. Of course, the added vdd series impedance must also be small enough in order that the DC drop from the DC MOS device drain current does not result in a significant voltage drop. Two possibilities to consider:

    1. Include a resistor from the analogLib in series with your vdd ideal supply and assign it a small DC resistance (1 milliohm?) and a large AC resistance (Rac >> rout, see Figure 2).

    2. Include a very large inductor from the analogLib in series with your vdd ideal supply. With a large enough value of inductance, at low frequencies its impedance may be set as >> the expected value of rout. The series inductor will not reduce the DC voltage of your vdd source, but at finite freuqencies, its impedance will prevent most of your input current from flowing through the DC source vdd.

    In both cases, change your DC source V2 to an AC current source with an AC value of 1 and a DC current of 0. Run the AC simulation. However, when you analyze the result, measure the real component of the voltage looking into the MOS drain node. Since the AC current source has a value of 1, the real part of the measured voltage will be the real impedance. You can extrapolate the real impedance, which is effectively rout(f),  to its value at DC from your measured result. There are other ways to measure rout, but this came to mind given your existing test bench.

    Let me know how you make out...

    Shawn

    FIgure 1

    Figure 2

  • in reply to ShawnLogan

    Hello Shawn it worked,Thanks :-)  

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