validating plot phase margin with STB simulation

OK, so it's not an "idial" (you meant "ideal" I assume) current source that you placed - it's an iprobe which is a current probe (there's an important difference here - an ideal current source would make the loop open loop whereas an iprobe is like a 0 V source).

You should plot the loop gain - it should be obvious from that (strong hint - both gates of your input diff pair are driven with ideal voltage sources, so the feedback is not going to be doing very much, which can probably be seen by the fact that your AC response has very high gain).

You really seem to struggle with the concepts of ideal voltage and current sources...

Andrew

Hello Andrew, Yes you are correct its not an current source but a current probe(very big difference regarding output ressistance).

Andrew Beckett said:

You should plot the loop gain

The open loop schematics and its results are shown bellow,beyong the AC response i added a transient response where we have 1V swing at the output.(as shown bellow)

So you are saying that for STB analisys i should remove my DC bias? Where should i put the iprobe in order to get the STB to show 60 degree result, as shown in the plot bellow?

Thanks

No, it's not a matter of needing to remove the DC bias for stability analysis. What I'm saying is that you're not actually setting a "bias' - you're actually forcing both inputs to be those DC levels, and so when you're simulating with a feedback loop, the feedback loop is not doing anything (which would be obvious from plotting the loop gain from the stability analysis). You probably need to do some research or speak to your supervisor about how opamps work or are used (any basic text should cover this - even wikipedia). If you had your OpAmp in a negative feedback configuration, and set the DC level on the non-feedback input, then the DC level of the other input would be controlled via the feedback circuit and should therefore end up close to the driven input without you needing to explicitly bias it with a source (it wouldn't be biased with a source in real life, so why do so in a simulation?)

This forum is not really here to teach you how to design basic circuits; some (such as Shawn) have shown a lot of patience in answering your questions, but you need to do some reading or learning to understand some of the basics, I think.

Kind Regards,

Andrew.

Hello Andrew, i understand my error.I tried to fix it by replacing the voltage forcing with  biasing by voltage divider from VDD=1.8V to 0.8 ,making exact 0.8V bias.(As shown bellow)

Afterwards i have put DC block capacitance on the "BIAS FORCING" voltage source in order the make them pass only potential 1V_AC voltage from one side.

The right source was removed totally later on and connected directly to the voltage divider bias.

In DC simulation i get perfect bias as before. However on the AC part unlike before i get a tottaly almost no response,as shown in the plot bellow.

Where did i go wrong passing the 1V AC signal from the left source?

Thanks.

You've shorted the two gates of the diff pair together, so it's hardly surprising there's no gain as the differential input signal is 0V. 

Andrew.

Hello Andrew , I have added another voltage divider for the purpose of  biasing the right input and i succseeded creating a response a before with the forced voltage .

Gain and Phase plots of the amplifier are shown bellow showing -311 degrees at 0dB which is 49 thus PM=180-49=131 , i have tried to put a current probe between the stages and defined the STB simulation as shown bellow, however i get again the NAN results in the stb summery.

Where did i go wrong?

Thanks

Dear robert21,

I am not finding the probe you inserted to perform the stability analysis in your schematic. You indicate it is between the first and second stages,  it I do not see it. Am I overlooking something? Clearly if the probe is  not included in the schematic, the results of a stability analysis will not be accurate.

Shawn

I do see an iprobe in the schematics shown above, bit since there doesn't appear to be any feedback. I can't see what use there would be in running a stability analysis. Stability analysis measures the loop gain, and from this loop gain it provides phase and gain margin of the feedback loop. In the configuration you have, your opamp is open loop, and operating it open loop is not terribly useful (unless you are trying to use it as a comparator). The biasing of the inputs is also a little odd. You're also still plotting the gain from the ac analysis, not the loop gain as was suggested earlier.

I would suggest (again) that you pay attention to the advice you've been given earlier (you seem to be trying out random things with little reference to any pointers you've been given), especially about speaking to your supervisor and reading some good texts on amplifier design and how to build practical circuits using opamps.

Regards,

Andrew.

Hello Andrew, I understand now that STB could not be used in open loop stability.

further more i  know that it is beyong the scope of the forum and i accept your ciritcue regarding my BIASING technique.

voltage divider with VDD was the only thing i came up with for replacing the dc voltage forcing.

The problem remained with the AC input,you didnt like my DC block system :-) i will try to look for other alternatives.

If you could please give me a hint or a link to the correct way of biasing the OPAMP and entering AC into it.

Thanks.