STB analysis of differential feedback amplifier

You have labelled both sides of the iprobe with the name vo_minus. This means that the iprobe is shorted output, as the error message indicates.

Remove the label on the gate to the right of the iprobe.

Andrew.

Hello Andrew , Yes after removing the right label ,it ran fine.

However, by comparing with the classical way of measuring phase margin.
The STB shows me 41 degrees phase margin,where as in the classical view shown in the plot,at 0dN i have -182 phase which means 2 degree PM.

My feedback probe connection is shown in the end(the vo_minus lable was removed).

How do we connect the probes for differential feedback in STB analysis?

Thanks.


AC analysis Phase margin:

STB analysis Phase margin:

I have no idea what you're comparing the stability analysis with - what this "classical way" you are describing is. You've plotted an ac response, but I have no idea what it's a plot of.

The only "classical" way I am aware of is that where you attempt to keep the loop closed during DC (to ensure that the operating point is found) and then open it during AC to measure the open loop gain at a particular point. That's usually achieved either using spectre's switch component (e.g the spt1switch), resistors which have a different AC resistance than DC resistance, or large inductors/capacitors. All of these approaches give the wrong answer because they do not load the circuit properly and can be very hard to implement using deeply embedded loops - stb analysis ensures that the loop stays closed at all points and measures the loop gain (it's like Middlebrook's method but with improvements which avoid the direction problems that Middlebrook's method has).

Anyway, I can't see what "differential" feedback you're talking about here (your schematics are rather badly drawn which makes them hard to follow too). You can measure differential and common-mode stability using the diffstbprobe component from analogLib and then the stb analysis can show you the stability for the differential or common-mode loop gain, but I'm not sure that's what you're asking.

Andrew.

Hello Andrew, i have implemented the folded cascode with common mode feedback shown bellow.

I tried to connect analogLib diffstbprobe on that common mode feedback differtial pair,for the stability of common mode and differential mode.

However,it gives me an error  shown in the end where i have a floating connection,although its connected to the gate of a transistor.

Where did i go wrong connecting diffstbprobe?

Thanks.

This is just because you have the inputs of the diffstbprobe connected to the inputs of the transistors (gates) so the schematic checker (which is quite a simple tool) thinking that nothing is driving the nets. I don't think these should matter because the direction of the probes don't really matter, but I think the probe would make more sense if flipped from left to right so that the outputs connect to the gates and that would also eliminate the warnings from the schematic checker.

BTW, if it was me, I'd take more care to align the transistors in the schematic and connect using wires rather than by name - it does tend to make the schematic much harder to follow.

Andrew.

Hello Andrew, i have rotate the probe like you said and it gave me the same error i had on the last problem where i didnt have any feedback loop.(which was solved when i connected the loop feedback,although it had a "forced" voltage supllies connected directly.)

However in here we connected a probe on the connected feedback loop.

What could cause this issue?
Thanks.

"Notice from spectre at freq = 500 MHz during STB analysis `stb'.
    Gain(dB)is always less than zero. The loop is always stable. No
gain margin or phase margin."

I would suggest plotting the loop gain (not sure if you're doing the stb analysis with differential or common-mode - that's a choice on the stb form) and seeing what that shows.

To be honest, I've not got the time (as I've said repeatedly) to keep debugging your setup and circuit; you need to find some assistance within your university, or contact customer support as looking at this from pictures alone is very time consuming.

Maybe somebody else on the forums can assist you further though.

Andrew.

Dear Robert21,

You have really not provided sufficient information to provide a complete answer to your stability issue. However, I believe I know the root cause of your issue without any detailed information as both Andrew and I have corrected so many of your prior issues.

You are not showing the DC operating points of any of your transistors not how you are generating the cascode bias voltages Vb2 or Vb3. I highly suspect that your bias conditions are not optimal for your folded cascode. The optimal biasing of folded cascode amplifiers is non-trivial. As a result of non-optimal biasing, I suspect your loop gain is not sufficient for any reasonable gain. This is my guess as to why your stability result suggests the differential gain is less than 0 dB.

Now, if I might add a note to you, please allow me some of your patience...

I, personally, believe I mentioned to you that as part of the learning process you need to study and think about your results before posting an item to request others to solve it for you. Without doing this, if you end up working in the field, you will never be able to solve a problem in your own. Now is the time to start - not after you find a position in a company.

So...

0. Write down a set of circuit requirements.

1. Study/correct and optimize your DC bias voltages and DC operating points.

2. Run a short transient analysis at some low frequency to verify your DC operating point is not hindering large signal performance.

3. Proceed to perform a stability analysis and verify the open loop gain is sufficient to meet circuit requirements.

Shawn