Plotting Output Capacitor of the MOSFET

Dear Hossein,

Hossein Eslahi said:

I think both approaches are correct and I should see the same behaviour, however, I see two different characteristics.

I am not positive I completely understand your two test bench examples. However, I think I do and have attached my understanding of your AC simulation test bench. There are two concerns that I believe need to be considered in your first analysis that, in my mind, will impact the accuracy of its capacitance estimate. 

1. The manner in which your gate bias is applied makes its source impedance 0 ohms. When examining the drain-source impedance, a current path exists from the drain to gate. With a zero gate impedance, this suggests that the current flowing through the gate-drain capacitance will be artificially high. It seems that you need to isolate the gate DC bias voltage with either an inductor, AC resistor, or some finite impedance to better assess the actual gate impedance in your application.

2. The expression you noted as:

Hossein Eslahi said:

mag(Id/(2Pi*f*Vac) t

does not appear to be correct. The current will have real and imaginary parts and you need to consider the imaginary only portion of the resulting impedance to estimate the effective capacitance. I note this in the attached figure of my understanding of your test bench.

For your reference, I have provided a test bench and means of estimating the C-V characteristics of an arbitrary circuit at the post:

community.cadence.com/.../capacitance-vs-bias-voltage-curve-for-ferroelectric-varactor

I also included the expressions to compute the effective capacitance and real impedance of the device under test. Perhaps this will provide some insight into estimating the effective  output capacitance of your device. 

I hope this helps...let me know if my comments are misdirected based on my understanding of your test bench and methodology.

Shawn

Thank you for your answer. I have used the imaginary part of the Id/(2*Pi*Vac*f) in AC simulation, but, the characteristics are still different. Here are my test-benches I used in Sp and AC simulations.

Dear Hossein,

Hossein Eslahi said:

I have used the imaginary part of the Id/(2*Pi*Vac*f) in AC simulation,

Ahah - that was not clear to me.  Thank you for the added information.

Hossein Eslahi said:

but, the characteristics are still different. Here are my test-benches I used in Sp and AC simulations.

I believe the drain impedances are different in your test bench. In the AC simulation, your driving impedance is 0 ohms. However, in your S parameter simulation, your driving impedance is the port impedance. 

Shawn

So, do you mean that the sp simulation is correct but the ac analysis is not valid?

Dear Hossein,

Hossein Eslahi said:

So, do you mean that the sp simulation is correct but the ac analysis is not valid?

I did not indicate if one or the other was not valid. Personally, I think having the zero gate impedance is not realistic of any "real" environment and that will cause the effective drain-source capacitance you measure in both case to be somewhat questionable of what you will observe in an actual application.

Irrespective of the gate impedance, an AC analysis can be quite accurate as that is what I use and have proven its accuracy in numerous simulations. I don't have a need to measure a C-V characteristic using an S parameter analysis.

Shawn