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Why don't PAE vs PT (Total Power) measurements agree?

FormerMember
FormerMember

Hello,

I'm tuning an NXP LDMOS FET model in Microwave Office.  When my Vds current is about 20A at 12V, my output power on port 2 measured by the "PT" Total Power measurement shows ~100W (which is our optimization target).  

Here is the part I don't understand:  Why does PAE show about 75%?    Shouldn't 100W/240W have a PAE of ~41%?

Port 1 (Pin) is 17dBm, so 0.050 Watts, a negligible amount. 

(Pout-Pin)/Pdc == (100-0.050)/240W == 0.416.

What am I missing here?

Thanks for your help!

-Eric

  • FormerMember
    FormerMember

    Here is some more info if someone is available to help:

    This  isa screenshot of the schematic and I've attached the .emp file.  

    There are two fets, a pre-amp using about 15mA and a power amp using 19.39 A.  

    Graph2 shows the current across the ideal DCVS's for the two drain-source's.  

    Graph3 shows the total power (PT) of port2 and PAE of port1,2. 

    Any idea why MWO is showing 75-82% PAE when my hand-calculation shows much less?

    The NXP models are available on the NXP site for these fets: 

    75watt-amp.zip

  • FormerMember
    FormerMember in reply to FormerMember

    Also note that ports 3,4,5,6 are just to confirm that the LC bias tee is minimizing RF leakage into the power supply.  DB[S3,1] through S6,1 are all <-60db.  They aren't involved in the amplification except to measure RF leakage.

  • FormerMember
    FormerMember in reply to FormerMember

    I made a PAE_Error output equation so when PAE_Error==1 there is no error.  >1 means AWR's PAE is too high, <1 means too low.  Interestingly, when I disabled the pre-amp fet (the first FET in the schematic) I am able to optimize and get PAE_Error=1.008, so its probably correct.  I wonder why it would be thrown off by the 2nd fet?

    Another anomaly is that the input port is 16.4dBm, the FET provides a 19.2 dB gain, which should be 3.6W of output---but PT_port2 shows 85W of output!  Why 85W?  I mean, I want that much output ultimately, but the S21 gain does not agree with the PT_port2 measurement that AWR is providing.

    Is this a problem in the way I am measuring in AWR or a problem with NXP's FET model?

  • FormerMember
    FormerMember

    Well, I've stripped it down to a single FET: Vds is 12V, Ids is 7.6A (91.2 W). PORT1/Pwr input to the FET is 36dBm (4W).  PT(PORT_2) says 15W, and PAE says 72.5% Efficient. The math for PAE just doesn't match the numbers. This is a bug, either in my understanding or in the program---I'm just not sure which. 

    I'm not sure what to do next, any help would be greatly appreciated!

    -Eric

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