Phase noise and jitter simulation

I have a clocking circuit containing 2 stages, a buffer followed by a divider. I used pss with shooting method +pnoise to simultate the Rj. Assume that the clock frequency is fin at the input of the buffer and fin/2 at the output of the divider. (fin is between 10~20GHz). The beat frequency is set to be fin/2 so that pss can converge.

Rj at the 1st stage output is then calculated in two ways:

1. Use Jee in the direct plot form. The integration range is 1M~fin/2 

2. Use Edge phase Noise in the same form to plot phase noise, and integrate the noise 1M~fin/2, convert it to Rj with respect to 2*pi*fin

Now the problem is that the Jee gives exactly twice the number of method 2. Does this mean that Jee rely on beat frequency to calculate the phase jitter instead of the real frequency?

When there are circuits operating in different frequencies, should users manually compensate the difference between beat frequency and real signal frequency if Jee is used to calculate Rj?