Question about DC convergence error in sweep simulation.

Dear Dongsuk,

> To see DC operating point, I did DC simulation, and it seemed like the values settled on wrong point. (Results were not reasonable.)

> 

> However, when I did sweep simulation (sweep variable was temperature, which should be almost non-relative to the results), I found DC convergence result goes to correctly as simulations goes on. - This is also weird and I couldn't understand.

> 

This is most often caused by multiple stable operating points. Hence, the solution found using a DC operating point may differ from that observed in a sweep analysis. 

1. Have you verified that your netlist has only a single stable operating point?

> I've already used nodeset, but it didn't worked.

2. Including a nodeset for a node in one's netlist will not necessarily assign the value you choose for the nodeset to the node. The value one assigns only serves as the starting value for its initial operating point analysis. If one wants to set the node to a specific value, one uses an initial condition as that will force the node to the value defined by the initial condition. In your example, if you have the exact node voltage from your sweep analysis, you might consider setting the node voltage using an initial condition to that exact value. 

However, I might suggest you study the circuit operating points from the DC operating point and sweep analysis to better understand the potential two stable operating points. Often, for this type of circuit, a peripheral "start-up" circuit is required to assure the operating point of the circuit is consistent with its design intention.

I hope this helps a little Dongsuk!

Shawn

Dear Shawn,

Thank you for the kind answers. As you know, I used nodeset first but it didn't worked, and after that I changed to writefinal -> readfile way and it somehow worked. Seems like this way is setting initial condition.

About the peripheral start-up circuits, as I know it was for transient simulation (like ramp-up power slowly ...). Is there any start-up circuit can be used for DC/AC-simulation?

Thank you so much!

Regards,

Dongsuk

Dear Dongsuk,

dskang said:

I used nodeset first but it didn't worked, and after that I changed to writefinal -> readfile way and it somehow worked. Seems like this way is setting initial condition.

If you inspect your input.scs file with the option selected, you will observe that, assuming you followed Andrew's suggestion, it will appear as a set of nodeset conditions for all of your net names.

dskang said:

About the peripheral start-up circuits, as I know it was for transient simulation (like ramp-up power slowly ...). Is there any start-up circuit can be used for DC/AC-simulation?

For a non-transient analysis, you will need to use the same approach as Andrew suggested in order to force the operating point to the state you desire. However, as Andrew noted and I think I did too, you should spend some time understanding why your circuit has multiple stable operating states and determining their potential root cause.

An alternative is to using a DC analysis prior to doing an AC gain analysis, you might consider running a transient analysis with your start-up circuit in place to achieve the desired operating state and then use the AC times feature. This will perform an AC analysis at one or more times in the transient analysis. Specific information on setting up a set of AC analyses within a transient analysis may be found at the Cadence On-line support site at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nSkaEAE&pageName=ArticleContent&oMenu=People%20who%20viewed%20this%20also%20viewed

I hope this provides some help Dongsuk!

Shawn

Dear Shawn,

Thank you again for the reply. I'll try what you said.

Have a nice day!

Regards,

Dongsuk

Dongsuk,

A little bit of advice, because I'm slightly concerned about the suggestion to use an initial condition rather than a nodeset. Using an initial condition with an ac analysis (via the readforce parameter, together with force=all or force=node) is nearly always a bad idea. Using a nodeset (via the readns parameter) is OK. You mentioned using readfile (which doesn't exist, so I'm not sure which you actually meant).

The reason why using initial conditions with an ac analysis is a bad idea is that you can use an initial condition to force the circuit to an incorrect/invalid operating point. If you do that in conjunction with a transient, the circuit will recover from the false start (it may take a while if the time constants are big, but it can recover). With an ac analysis, it merely does a small-signal analysis at the point the circuit has been forced to (that's why the terminology force is used), and that could be complete garbage. With a nodeset however, that's a starting point for the convergence algorithm and it first tries to reach convergence with the nodeset applied, and then the node sets are removed and it tries to continue to reach convergence without them - which means that a genuine operating point can be reached.

Normally (by default) initial conditions are ignored by ac and dc analyses (transient honours them by default) unless you go out of your way to enable the force.

However, as both Shawn and I have said, the right thing to do here is make sure you understand the reason for alternative stable operating points, because it may point to an undesirable feature of your circuit (or models) that you weren't expecting to be part of the design.

Regards,

Andrew

Dear Andrew,

I wrote incorrectly : readfile -> readforce. So I was using initial condition, which was the last settled DC convergence value during DC sweep.

As you said, it may leads to false results. But when using nodeset, it went back to false results again when AC simulation begins. Still this part is hard to understand.

So I just enabled the force=all and used initial condition setting for all internal nodes, as far as I know it was only way that DC converge results can be at that points (unless I fix verilog-A code).

Still, the DC convergence results(what I've used as initial condition) seems reasonable if looking at transistor by transistor, and also they looks good as a whole circuit - Kirchhoff laws-. 

Even under above situation, will it still be dangerous to use initial condition to do AC simulation?  

Thank you again :)

Regards,

Dongsuk

Dear Andrew,

About AC simulation, I changed readforce to readns (I didn't know about readns, I just learned it from documents): so now I think I'm using nodeset instead of initial condition. And it seems like working.

Maybe I was wrong somehow in manually inserting all node's nodeset.

Thank you.

Regards,

Dongsuk

Dear Dongsuk,

dskang said:

I'm using nodeset instead of initial condition. And it seems like working.

Perfect! This is the best way to assure the solution is one that provides the proper DC operating point for an AC small-signal analysis

dskang said:

So I just enabled the force=all and used initial condition setting for all internal nodes, as far as I know it was only way that DC converge results can be at that points (unless I fix verilog-A code).

Still, the DC convergence results(what I've used as initial condition) seems reasonable if looking at transistor by transistor, and also they looks good as a whole circuit - Kirchhoff laws-. 

Even under above situation, will it still be dangerous to use initial condition to do AC simulation?  

I do not want to speak for Andrew, but I believe there is still an issue with using a set of initial conditions for two reasons. See what you think...

1. Using a set of initial conditions for every node (as you have done) with the force option will set the voltages at each node to the value you set and not necessarily to the precise voltages to exactly satisfy the network equations. Hence, the operating point of the devices may not exactly correspond to those in the actual solution. This may be important in, for example, high-gain amplifiers with feedback as the difference in voltages between their "reference" and "feedback" node voltages may be very small - but important.

2. Using the set of initial conditions is also inherently "hiding" the presence of the alternate stable state. It is typically important to identify these states early in a design to either understand or eliminate them. In my opinion only. 'hiding" their presence by ignoring them and analyzing the AC performance under the desired stable solution is likely not the most time efficient way to arrive at an optimized design.

Shawn

Dear Shawn,

Thank you for answering my question. Now I understand some degree how to handle this problem. It's lucky that I could find solution, even it is not 100% orthodox - like fixing code.

Your advice helped me a lot. Thank you again:)

Regards,

Dongsuk

Dear Dongsuk,

You are most welcome - but I am just happy to read that you have a better understanding and have some time of solution to your problem! Thank you for letting Andrew and I know!

Shawn

Dear Dongsuk,

You are most welcome - but I am just happy to read that you have a better understanding and have some time of solution to your problem! Thank you for letting Andrew and I know!

Shawn