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  3. PSS does not converge if initial condition is set

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PSS does not converge if initial condition is set

jandk
jandk over 3 years ago

  When I simulate a divider as shown in the circuit diagram below, I find that if I don't give the initial state of the circuit shown in the diagram, the circuit doesn't achieve its function("1"  for high voltage 1.2V, "0" for gnd 0V). I set the initial condition in ADE simulation>>convergence aids>>initial condition. The problem is that if I set the initial condition, PSS does not converge and if I don't set the initial condition, the PSS converges but the circuit does not work(circuit nodes do not see any level changes).  And I find that Conv norm keeps the value of 606e+03 constant. So how do I set it up to make the PSS converge? 

Look forward to your reply.

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  • Andrew Beckett
    Andrew Beckett over 3 years ago

    The convergence problem is probably that you don't have the PSS fundamental frequency set correctly, or that you didn't give a long enough time for the tstab to ensure the divider is correctly working. I don't quite see from the above what the circuit is supposed to be doing (since it appears to be a shift register rather than a divider. If it's a divider, did you set the PSS frequency to the divided down frequency (rather than the input frequency)? Are there any even lower frequencies in the circuit (sub-harmonics)? If so, your PSS fundamental needs to reflect that as all frequencies in the circuit need to be an integer multiple of the PSS fundamental.

    Andrew

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  • jandk
    jandk over 3 years ago in reply to Andrew Beckett

    That right! You have pointed out the problem that I didn't notice the lowest frequency was changed to one eighth of the original frequency. Thank you very much!

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  • ShawnLogan
    ShawnLogan over 3 years ago in reply to jandk

    Dear jandk,

    jandk said:
    nd if I don't set the initial condition, the PSS converges but the circuit does not work(circuit nodes do not see any level changes). 

    I fear a second issue may be that without your initial condition, the circuit (which appears to be a divider), is that the circuit will not function unless you ensure the output of one flip-flop has a different state than the remaining flip-flop outputs. For example if all outputs come up in the logic low state, as the input clock advances, all the flip-flops will remain in the logic low state and hence will not form a divide-by-8 of the input clock frequency.

    Shawn

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  • jandk
    jandk over 3 years ago in reply to ShawnLogan

    That's right. If I don't give the initial logic state, all nodes will keep the same voltage level all the time. 

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