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LVS fails after partial layout extraction with EMX

GSBif

Hi,

I am trying to implement a design flow where I can simulate parts of my circuit with EMX (e.g. an instance of a custom made inductor), and the remaining parts with parasitic extraction. For this I have been following the RAK "Virtuoso RF Solution: IC Layout Electromagnetic Simulation." In particular, modules 3 and 4 of this RAK should contain what I need. I have followed module 3 for one of my designs without problems, in which I select a specific instance in my layout and get it extracted with EMX, and produce an extracted view. The problem comes in module 4 when doing LVS on the circuit. LVS using both Assura and PVS fails, with PVS prompting the following: ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'auCdl schematic', for the instance ...

The instance I am simulating has no schematic view, but just a layout and custom made symbol. After simulation with EMX, an em_extracted view is added as well. The difference between the example in the RAK and my own circuit is that while the instance from the RAK has no schematic either, it does have "auCdl" and "auLvs" views. After reading about somehow similar issues in the forum, I went on and copied my symbol to both of these views. LVS seems to move forward a little bit further, but still fails and prompts: ERROR (NVN-13010): Cell ... is not defined. 

I guess something else has to be defined (something is mentioned in the forum about editing "CDF") but I am not sure what. I am still rather new to Cadence, so I find this all a bit confusing. What I need from LVS here is just to acknowledge that there is layout connectivity to this instance as specified in the schematic, but whatever is on the instance itself is being modeled by the EMX extraction. If anyone can shine some light or give a hint on how to proceed, it would be much appreciated.

Thanks and best regards,

GSBif

  • Update: I made some further progress although I am not there yet. I went into CIW->Edit->CDF, selecting "CDF layer" as "base", and in Simulation Information I selected auLvs and set a name under componentName (matching the name if my instance in the schematic I am working with). Now LVS completes only with Assura, but it is reading through my custom made component, that is, it takes the layout and tries to match with schematic, and complains that it cannot find the components in the schematic. I think what I am missing here is just a way to tell LVS to stop at the ports of this instance and not look inside. Any clues?

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