Calibre Quantus for RC extraction of varactors

This is probably more of a question for the foundry that provides the rule decks you're using, but I'd start by looking at the resulting spectre netlist (compare pre-layout and post-layout) to see if there's an instance of the varactor. I would expect that if this was working, the varactor would be identified by LVS and then appear in the post-layout netlist as a specific component. It's not a matter of picking an output type that Quantus will deal with this appropriately (Quantus knows nothing about the designed devices; those are recognised by your LVS rule deck and parameters extracted for them by the LVS deck). 

Andrew

Dear Yussef,

Youssef Bendou said:

A simulation of the varactor in schematic view with Spectre shows that my capacitance changes between 190 fF and 450 fF when I change the DC voltage around my varactors, but when I add the dspf file generated by Quantus, my capacitance drops to 1 fF independently of the DC voltage value

Youssef Bendou said:

Could someone advise me on what output type I should choose for something like a varactor, which is not a transistor but also technically not a passive element ?

I am basically agreeing with Andrew's comment, but I may be able to add a bit more insight into why you are observing the simulation results using the DSPF view relative to the schematic view. As you correctly mentioned, the conventional MOS varactor does not use the dame doping profile as does a conventional MOS device. Basically, to achieve the large capacitance sensitivity to voltage, the doping profile sets the net capacitance as the series combination of a MOS gate oxide (relatively large, say Cox) and the capacitance of its inverted channel (relatively small, say Cinv). Hence, as the voltage across the channel changes, the overall capacitance changes from Cinv to Cox as the region below the MOS gate changes from an accumulated region (capacitance Cox) to an inverted region (Cinv). Withe net capacitance of C = Cox || Cinv, the resulting nonlinear C-V capacitance characteristic provides a reasonable "varactor" characteristic. A conventional transistor never provides a fully accumulated channel beneath its MOS gate and hence its capacitance-voltage characteristic will not provide the voltage sensitivity of an MOS varactor structure. As a result, my guess is the resulting model for your varactor is being called correctly in a schematic view, but the model for the foundry (used in the DSPF view) is not correct and corresponds to a conventional transistor.

This MOS capacitance-voltage effect was first studied and reported in some detail by Mr. A. Goetzberger in reference [1 and can be obtained from the IEEE if you have an appropriate membership.

If you have further interest in the details of the structure and how its profile differs from a conventional MOS transistor doping profile, you might be interested in the description at the public document at URL:

https://pdfpiw.uspto.gov/.piw?PageNum=0&docid=04973922&IDKey=9D1FFD9CD331&HomeUrl=http%3A%2F%2Fpatft.uspto.gov%2Fnetacgi%2Fnph-Parser%3FSect1%3DPTO2%2526Sect2%3DHITOFF%2526p%3D1%2526u%3D%25252Fnetahtml%25252FPTO%25252Fsearch-bool.html%2526r%3D1%2526f%3DG%2526l%3D50%2526co1%3DAND%2526d%3DPTXT%2526s1%3D4%2C973%2C922.PN.%2526OS%3DPN%2F4%2C973%2C922%2526RS%3DPN%2F4%2C973%2C922

I hope this helps a little Youssef!

Shawn

[1] A. Goetzberger, "Ideal mos curves for silicon," in The Bell System Technical Journal, vol. 45, no. 7, pp. 1097-1122, Sept. 1966, doi: 10.1002/j.1538-7305.1966.tb01689.x.

Dear Yussef,

Youssef Bendou said:

A simulation of the varactor in schematic view with Spectre shows that my capacitance changes between 190 fF and 450 fF when I change the DC voltage around my varactors, but when I add the dspf file generated by Quantus, my capacitance drops to 1 fF independently of the DC voltage value

Youssef Bendou said:

Could someone advise me on what output type I should choose for something like a varactor, which is not a transistor but also technically not a passive element ?

I am basically agreeing with Andrew's comment, but I may be able to add a bit more insight into why you are observing the simulation results using the DSPF view relative to the schematic view. As you correctly mentioned, the conventional MOS varactor does not use the dame doping profile as does a conventional MOS device. Basically, to achieve the large capacitance sensitivity to voltage, the doping profile sets the net capacitance as the series combination of a MOS gate oxide (relatively large, say Cox) and the capacitance of its inverted channel (relatively small, say Cinv). Hence, as the voltage across the channel changes, the overall capacitance changes from Cinv to Cox as the region below the MOS gate changes from an accumulated region (capacitance Cox) to an inverted region (Cinv). Withe net capacitance of C = Cox || Cinv, the resulting nonlinear C-V capacitance characteristic provides a reasonable "varactor" characteristic. A conventional transistor never provides a fully accumulated channel beneath its MOS gate and hence its capacitance-voltage characteristic will not provide the voltage sensitivity of an MOS varactor structure. As a result, my guess is the resulting model for your varactor is being called correctly in a schematic view, but the model for the foundry (used in the DSPF view) is not correct and corresponds to a conventional transistor.

This MOS capacitance-voltage effect was first studied and reported in some detail by Mr. A. Goetzberger in reference [1 and can be obtained from the IEEE if you have an appropriate membership.

If you have further interest in the details of the structure and how its profile differs from a conventional MOS transistor doping profile, you might be interested in the description at the public document at URL:

https://pdfpiw.uspto.gov/.piw?PageNum=0&docid=04973922&IDKey=9D1FFD9CD331&HomeUrl=http%3A%2F%2Fpatft.uspto.gov%2Fnetacgi%2Fnph-Parser%3FSect1%3DPTO2%2526Sect2%3DHITOFF%2526p%3D1%2526u%3D%25252Fnetahtml%25252FPTO%25252Fsearch-bool.html%2526r%3D1%2526f%3DG%2526l%3D50%2526co1%3DAND%2526d%3DPTXT%2526s1%3D4%2C973%2C922.PN.%2526OS%3DPN%2F4%2C973%2C922%2526RS%3DPN%2F4%2C973%2C922

I hope this helps a little Youssef!

Shawn

[1] A. Goetzberger, "Ideal mos curves for silicon," in The Bell System Technical Journal, vol. 45, no. 7, pp. 1097-1122, Sept. 1966, doi: 10.1002/j.1538-7305.1966.tb01689.x.

Hello Andrew, Hello Shawn,

Thank you very much for your comments and insights, I have been trying to fix the problem the past two days and I haven't succeeded. I did compare the netlists generated by ADE before layout and post-layout and it seems that the tool is calling the varactor instances correctly so maybe I was wrong with my assumption. I requested help from the foundry that provided the DK, I hope they can help me with this.

Thank you again !

Youssef