Dynamic latch comparator

Dear sounakd01,

sounakd01 said:

Can anyone please suggest

me how to calculate the kickback noise voltage and clock-feed-through voltage of Dynamic latch comparator in CADENCE?

I am little confused as to what you specifically are trying to estimate - sorry! Let me try to provide a few thoughts at the risk of them not being helpful.

Both the kickback noise and clock feed-through can be observed in a transient simulation, it seems performing a set of transient simulations under different sets of process and environmental conditions will provide a range of both values. 

Since both simulations are highly dependent on the output impedances of the input and clock signals applied to the latch, I would recommend using the actual drivers  in your simulation (i.e., do not use an ideal source for either). Since these two parameters are also very sensitive to the parasitic capacitances between nodes, an accurate estimate of the two effects requires the use of a layout based netlist. A schematic representation will not provide an accurate estimate.

If you do not have a layout from which an extracted view can be generated or are unsure of the clock and input signal drivers, an alternative is to run a set of simulations with the driving source impedances (resistance/capacitance) and parasitic coupling capacitances as variables and sweep their values. This might provide some insight into the sensitivity of the kickback noise and clock feedthrough to these parameters. This can be useful information when realizing your circuit in layout.

I hope this provides the type of information you were hoping sounakd01.

Shawn