• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. RF Design
  3. PNOISE Noise Type Time Average vs. Sampled Jitter

Stats

  • Replies 8
  • Subscribers 62
  • Views 2696
  • Members are here 0

PNOISE Noise Type Time Average vs. Sampled Jitter

AB_1719406998389
AB_1719406998389 2 months ago

I am new to the sampled jitter noise type in Pnoise simulation and I want to compare the results between time average and sampled jitter settings. My testbench is very simple, a square wave input at 8G and a 4 stage differential inverter buffer. The fanout ratio is 2 and I am looking at the differential noise at the output of stage 1,2 and 3. The otuputs are all square wave-ish. The time-domain waveform at input and stage 1,2,3 outputs are as following snapshot.

Then I started to compare noise results. Here I compare the differential noise at stage 1,2,3 output, in two forms. The first is the output noise (dBc/Hz) - PM - DSB with time average setting. The second is the edge phase noise (dBc/Hz) with sampled jitter. The trigger is at the rising edge of the the difference between the differential signals and set at when it crosses zero. I found the noise results between these two settings are very similar. They are attached at the following snapshot. The solid lines are results from time average, the dashed are from sampled jitter. The graphes from left to right are results at stage 1,2 and 3 output.

My understanding is like this. For buffers with sharper edges, most of the noise is phase noise and the crossing point has the worst jitter, or phase noise. In that case, the time average and sample jitter should give similar results. If the edges are not that sharp, then sampled jitter should give worse results as it is really looking at the worst point while time average should give better results as it is averaged within a cycle. But here sampled jitter seems to give a phase noise similar to a DSB output noise from time average. So result from sampled jitter is 3dB worse if we are talking about phase noise as it is defined as SSB. This is very confusing for me, especially it is almost exactly 3dB. Can any one help me to point out if I am mixing different things? or the way to understand the edge phase noise result from sampled jitter setting. Thanks!

  • Cancel
  • Sign in to reply
  • JankoK
    JankoK 2 months ago

    Hi,

    Note that with noisetype=timeaverage, you are averaging across the whole cycle, both states and both edges. On the other hand, with noisetype=sampled, you are measuring at that specific threshold point of rising edge. Perhaps falling edge carries more noise in your case. You should plot that one too for fair comparison. There is a nice article that covers this: 

    Why is pnoise sampled(jitter) different than pnoise timeaverage on a driven circuit?

    If that's not the case, you should perhaps revisit your setup. Abrupt edges in combination with high frequency sometimes require very high noisefmax (and even number of harmonics/sidebands) for accurate results. As a rule of thumb, you can use 1/risetime as a starting point, which ends up being around 100G in your case. Start there and then increase it until you see no changes in your noise results. 

    Hope this helps!

    /Janko

       

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Cancel
  • AB_1719406998389
    AB_1719406998389 2 months ago in reply to JankoK

    Hi Janko

    Thanks for your message!

    Sorry forgot to include in the post that noise at rising edge and falling edge are very similar. For noisefmax, I put a harmonic of 50 in the PSS setup so that should cover beyond 400G. The snapshot of my PSS, timeaverage Pnoise and sampled jitter Pnoise is as following snapshot.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • AB_1719406998389
    AB_1719406998389 2 months ago in reply to AB_1719406998389

    thanks again for your help

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • JankoK
    JankoK 2 months ago in reply to AB_1719406998389

    Yes, 50 is more than enough... with 8.4G frequency, 100G noisefmax equivalent would be like 12 harmonics.

    Looking at you setup... your stop frequency is too low. You are cutting 3/4 of contributors. It should be 4.2G (half fundamental). There used to be an article that explains the reasoning but its being revoked for updating. There is this one that mentions it:

    How to reconcile the linear noise, pnoise, and transient noise results on a switched capacitor ckt?

    The rest seems ok to me.

    /Janko

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Cancel
  • JankoK
    JankoK 2 months ago in reply to JankoK

    By the way, if you are using our standard expressions (from Direct Plot) for Phase Noise (time averaged) and Edge Phase Noise (sampled), they are both SSB. If you are to run transient and do PN() you would end up with DSB. Then you would need to subtract or add 3.01dB to get the matching. 

    /Janko

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • AB_1719406998389
    AB_1719406998389 2 months ago in reply to JankoK

    thanks for the message.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • Tawna
    Tawna 2 months ago

    Thank you, Janko, for your responses. 

    To the original poster:  You may also want to look at this Article Pnoise/hbnoise: Frequently asked questions on https://support.cadence.com.   It contains important information on  the various pnoise/hbnoise settings and how to determine when your simulation result is accurate.

    Best regards,

    Tawna 

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • Tawna
    Tawna 2 months ago in reply to JankoK

    If simulating pnoise sampled(jitter), set the pnoise stop frequency to 1/2 pss_fundamental.   There are a couple of articles that mention this:

    How can I set the stop frequency for a sampled pnoise/hbnoise analysis to be half the PSS fundamental?

    The mathematics behind choosing the upper frequency when simulating pnoise jitter on an oscillator 

    If simulating a divider or multiplier, follow the guidelines here:

    How to set up pss/pnoise sampled(jitter) when simulating a driven circuit or a VCO, both containing dividers  

    How to simulate a Frequency Multiplier (x2) in SpectreRF Shooting Newton PSS 

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information