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  • Discussion

    add a time interval (delay) in a loop

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    Latest over 14 years ago
    by SkilSiao
  • Discussion

    Error initializing COM property pages Doing netlist with cadence 16.3 under windows 7 Locked

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    1 reply
    Latest over 14 years ago
    by oldmouldy
  • Discussion

    Looking for PCB designer with v15.7 to help with several small layout projects Locked

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    2 replies
    Latest over 14 years ago
    by pcbemc
  • Discussion

    what is my best way to combine two files? Locked

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    6 replies
    Latest over 14 years ago
    by pcbemc
  • Discussion

    Check for crossing segments before axlDBCreateShape

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    2 replies
    Latest over 14 years ago
    by eDave
  • Discussion

    Design approach Locked

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    by purikku22
  • Discussion

    pcb editor 16.3 problem Locked

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    0 replies
    Started over 14 years ago
    by Dtlmass
  • Discussion

    Selecting Allegro PCB Editor parts from OrCAD file Locked

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    3 replies
    Latest over 14 years ago
    by Mstrghettorigg
  • Discussion

    Create component

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    6 replies
    Latest over 14 years ago
    by Ejlersen
  • Discussion

    Design Rule Check Error Locked

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    1 reply
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    by pcb viet nam
  • Discussion

    Hiring PCB Layout Designer Locked

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    2 replies
    Latest over 14 years ago
    by pcb viet nam
  • Discussion

    Design Reuse - module nets turn to "dummy nets" and ref des not grabbing suffix - Allegro 16.5 (Design Entry HDL) Locked

    408 views
    0 replies
    Started over 14 years ago
    by KoolKat
  • Discussion

    Migrating old .llb footprints_delete "IS2" layer Locked

    1071 views
    4 replies
    Latest over 14 years ago
    by engineer123
  • Discussion

    free software cadence allegro Locked

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    3 replies
    Latest over 14 years ago
    by oldmouldy
  • Discussion

    how to handle illegal characters when reading a file

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    5 replies
    Latest over 14 years ago
    by Ejlersen
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