Stats

  • Locked Locked
  • Replies 0
  • Subscribers 164
  • Views 394
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Design Reuse - module nets turn to "dummy nets" and ref des not grabbing suffix - Allegro 16.5 (Design Entry HDL)

KoolKat

I place one of my reuse modules in the top-level board but many of the module nets turn to "dummy nets" and on many of the components the assigned Suffix on the Reference Designators are not there.  Some parts have the suffix but many do not.

Using SUBDESIGN_SUFFIX (0-6) as an attribute on each reuse instance in the schematic DEHDL.  Upon packaging --- using "Force Subdesign", "Create Subdesign" is empty.

Has anyone witnessed this problem?  Thank you, in advance, for any suggestions.

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.